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AM1808AZWT4

更新时间： 2024-11-07 06:36:59
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德州仪器 - TI 微处理器
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264页 1764K
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AM1808 ARM Microprocessor

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AM1808  
www.ti.com  
SPRS653–FEBRUARY 2010  
AM1808 ARM Microprocessor  
Check for Samples: AM1808  
1 AM1808 ARM Microprocessor  
1.1 Features  
12  
Interfaces  
• 375/456-MHz ARM926EJ-S™ RISC MPU  
• ARM926EJ-S Core  
• Two Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– Single Cycle MAC  
• One Host-Port Interface (HPI) With 16-Bit-Wide  
Muxed Address/Data Bus For High Bandwidth  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
– ARM® Jazelle® Technology  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– Two Independent Programmable Realtime  
Unit (PRU) Cores  
•
•
•
•
32-Bit Load/Store RISC architecture  
4K Byte instruction RAM per core  
512 Bytes data RAM per core  
PRU Subsystem (PRUSS) can be disabled  
via software to save power  
– 2 Channel Controllers  
– 3 Transfer Controllers  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
•
Register 30 of each PRU is exported from  
the subsystem in addition to the normal  
R31 output of the PRU cores.  
– Standard power management mechanism  
– Programmable Transfer Burst Size  
• 128K-Byte On-chip Memory  
• 1.8V or 3.3V LVCMOS IOs (except for USB and  
DDR2 interfaces)  
•
•
Clock gating  
Entire subsystem under a single PSC  
clock gating domain  
– Dedicated interrupt controller  
• Two External Memory Interfaces:  
– EMIFA  
– Dedicated switched central resource  
• USB 1.1 OHCI (Host) With Integrated PHY  
(USB1)  
• USB 2.0 OTG Port With Integrated PHY (USB0)  
– USB 2.0 High-/Full-Speed Client  
– USB 2.0 High-/Full-/Low-Speed Host  
– End Point 0 (Control)  
•
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
16-Bit SDRAM With 128 MB Address  
Space  
– DDR2/Mobile DDR Memory Controller  
•
16-Bit DDR2 SDRAM With 512 MB  
Address Space or  
– End Points 1,2,3,4 (Control, Bulk, Interrupt or  
ISOC) Rx and Tx  
•
16-Bit mDDR SDRAM With 256 MB  
Address Space  
• One Multichannel Audio Serial Port:  
– Transmit/Receive Clocks  
• Three Configurable 16550 type UART Modules:  
– With Modem Control Signals  
– 16-byte FIFO  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– DIT-Capable  
– 16x or 13x Oversampling Option  
• LCD Controller  
• Two Serial Peripheral Interfaces (SPI) Each  
With Multiple Chip-Selects  
• Two Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
– FIFO buffers for Transmit and Receive  
• Two Multichannel Buffered Serial Ports:  
– Transmit/Receive Clocks  
– Two Clock Zones and 16 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– AC97 Audio Codec Interface  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
ARM926EJ-S is a trademark of ARM Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
Copyright © 2010, Texas Instruments Incorporated  
 
 
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