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AM1808ZCED3

更新时间： 2024-11-24 06:36:59
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德州仪器 - TI 微处理器
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264页 1777K
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AM1808 ARM Microprocessor

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AM1808  
www.ti.com  
SPRS653A–FEBRUARY 2010–REVISED APRIL 2010  
AM1808 ARM Microprocessor  
Check for Samples: AM1808  
1 AM1808 ARM Microprocessor  
1.1 Features  
12  
• Highlights  
• Two External Memory Interfaces:  
– EMIFA  
– 375/456-MHz ARM926EJ-S™ RISC Core  
– ARM9 Memory Architecture  
– Programmable Real-Time Unit Subsystem  
– Enhanced Direct-Memory-Access Controller  
3 (EDMA3)  
•
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
16-Bit SDRAM With 128 MB Address  
Space  
– Two External Memory Interfaces  
– DDR2/Mobile DDR Memory Controller  
– Three Configurable 16550 type UART  
Modules  
•
16-Bit DDR2 SDRAM With 512 MB  
Address Space or  
– Two Serial Peripheral Interfaces (SPI)  
– Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
•
16-Bit mDDR SDRAM With 256 MB  
Address Space  
• Three Configurable 16550 type UART Modules:  
– With Modem Control Signals  
– 16-byte FIFO  
– 16x or 13x Oversampling Option  
• LCD Controller  
– Two Master/Slave Inter-Integrated Circuit  
– USB 2.0 OTG Port With Integrated PHY  
– One Multichannel Audio Serial Port  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– Three 64-Bit General-Purpose Timers  
– One 64-bit General-Purpose/Watchdog Timer  
– TwoEnhanced Pulse Width Modulators  
– Three 32-Bit Enhanced Capture Modules  
• 375/456-MHz ARM926EJ-S™ RISC MPU  
• ARM926EJ-S Core  
• Two Serial Peripheral Interfaces (SPI) Each  
With Multiple Chip-Selects  
• Two Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
Interfaces  
• Two Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
• One Host-Port Interface (HPI) With 16-Bit-Wide  
Muxed Address/Data Bus For High Bandwidth  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– Single Cycle MAC  
– ARM® Jazelle® Technology  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– Two Independent Programmable Realtime  
Unit (PRU) Cores  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
•
•
•
•
32-Bit Load/Store RISC architecture  
4K Byte instruction RAM per core  
512 Bytes data RAM per core  
PRU Subsystem (PRUSS) can be disabled  
via software to save power  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– 2 Channel Controllers  
– 3 Transfer Controllers  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
•
Register 30 of each PRU is exported from  
the subsystem in addition to the normal  
R31 output of the PRU cores.  
– Standard power management mechanism  
•
•
Clock gating  
Entire subsystem under a single PSC  
clock gating domain  
– Programmable Transfer Burst Size  
• 128K-Byte On-chip Memory  
• 1.8V or 3.3V LVCMOS IOs (except for USB and  
DDR2 interfaces)  
– Dedicated interrupt controller  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
ARM926EJ-S is a trademark of ARM Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
Copyright © 2010, Texas Instruments Incorporated  
 
 
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