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AK68512D/3.3-70 PDF预览

AK68512D/3.3-70

更新时间: 2024-11-07 14:49:43
品牌 Logo 应用领域
ACCUTEK 静态存储器
页数 文件大小 规格书
2页 85K
描述
SRAM

AK68512D/3.3-70 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:compliant风险等级:5.8
Base Number Matches:1

AK68512D/3.3-70 数据手册

 浏览型号AK68512D/3.3-70的Datasheet PDF文件第2页 
Accutek  
Microcircuit  
Corporation  
AK68512D  
524,288 x 8 Bit CMOS  
Static Random Access Memory  
DESCRIPTION  
The Accutek AK68512D high density memory module is a static  
random access memory organized in 512K x 8 bit words. The as-  
sembly consists of two medium speed 128K x 8 SRAMs in thin  
TSOP packages and a CMOS decoder logic IC mounted on the top  
side and two medium speed 128K x 8 SRAMs in thin TSOP pack-  
ages mounted on the bottom surfaces of a printed circuit board.  
The module is supplied in a 600 mil wide,32 pin DIP (Dual In-Line  
Package) configuration. This pinout is completely compatible with  
forthcoming industry standard monolithic designs. These modules  
are intended for use in applications where limited board space dic-  
tates compact module designs.  
The operation of the AK68512D is identical to standard monolithic 8  
bit word wide SRAMs.  
The AK68512D offers the features of low power and medium speed  
by using CMOS devices and makes high density mounting possible  
with no surface mount technology.  
FEATURES  
· 524,288 x 8 bit organization  
ELECTRICAL SPECIFICATIONS  
· Fast access time: 85 - 120 nSEC  
Timing diagrams and basic electrical characteristics are those of  
the standard 128K x 8 SRAMs used to construct these modules.  
Accutek’s module design allows the flexibility of selecting indus-  
try-compatible 128K x 8 SRAMs from any of a number of semicon-  
ductor manufacturers.  
· Completely static RAM, no clock or timing strobe required  
· Inputs and outputs TTL compatible  
· Conventional 600 mil wide SIP package with industry  
compatible pinout  
· Single 5 volt power supply - AK68512D  
· Single 3.3 volt power supply - AK68512D/3.3  
· Operating free air temperature 00 to 700C  
PIN NOMENCLATURE  
PIN ASSIGNMENT  
DQ1 - DQ8  
A0 - A18  
CE  
Data In/Data Out  
Adress Inputs  
Chip Enable  
Write Enable  
5v Supply  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
DQ1  
DQ2  
DQ3  
VSS  
VCC  
A15  
30 A17  
32  
31  
1
2
3
4
5
6
7
8
WE  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE  
DQ8  
DQ7  
DQ6  
DQ5  
DQ4  
Vcc  
Vss  
Ground  
OE  
Output Enable  
9
10  
11  
12  
13  
14  
15  
16  
TIMING OPTIONS  
70 nSEC Access Time  
85 nSEC Access Time  
100 nSEC Access Time  
120 nSEC Access Time  
Top View  

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