Datasheet > AK68512D1C/3.3-55

AK68512D1C/3.3-55

更新时间： 2024-09-18 14:32:47

品牌	Logo	应用领域
ACCUTEK		静态存储器
页数	文件大小	规格书
2页	128K
描述
SRAM

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技术参数
数据手册

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AK68512D1C/3.3-55 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.8
Is Samacsys：	N	Base Number Matches：	1

AK68512D1C/3.3-55 数据手册

AK68512D1C

524,288 x 8 Bit CMOS

Static Random Access Memory

ACCUTEK

MICROCIRCUIT CORPORATION

DESCRIPTION

The Accutek AK68512D1C high density memory module is a static

random access memory organized in 512K x 8 bit words. The as-

sembly consists of one medium speed 512K x 8 SRAM in a TSOP

Type 2 package. The module is supplied in a 600 mil wide, 32 pin

DIP (Dual In-Line Package) configuration. This pinout is completely

compatible with industry standard monolithic designs. These mod-

ules are intended for use in applications where limited board space

dictates compact module designs.

The operation of the AK68512D1C is identical to standard mono-

lithic 8 bit word wide SRAMs.

The AK68512D1C offers the features of low power and medium

speed by using CMOS devices and makes high density mounting

possible with no surface mount technology.

FEATURES

· 524,288 x 8 bit organization

ELECTRICAL SPECIFICATIONS

· Fast access time: 55 - 70 nSEC

Timing diagrams and basic electrical characteristics are those of

the standard 512K x 8 SRAMs used to construct these modules.

Accutek’s module design allows the flexibility of selecting indus-

try-compatible 512K x 8 SRAMs from any of a number of semicon-

ductor manufacturers.

· Completely static RAM, no clock or timing strobe required

· Inputs and outputs TTL compatible

· Conventional 600 mil wide SIP package with industry

compatible pinout

· Single 5 volt power supply - AK68512D1C

· Single 3.3 volt power supply - AK68512D1C/3.3

· Operating free air temperature 0⁰to 70⁰C

PIN NOMENCLATURE

PIN ASSIGNMENT

FUNCTIONAL DIAGRAM

DQ₁- DQ₈

A₀- A₁₈

Data In/Data Out

Adress Inputs

Chip Enable

Write Enable

5v Supply

A18

A16

A14

A12

Vcc

A15

A17

A13

A₁₈

A₁₆

A₁₄

A₁₂

A₇

V_CC

A₁₅

A₁₇

A₁₃

Vcc

Vss

Ground

A₆

A₈

Output Enable

A₅

A₉

A11

A₄

A₁₁

A₃

A₁₀

A10

TIMING OPTIONS

A₂

DQ8

DQ7

DQ6

DQ5

DQ4

A₁

55 nSEC Access Time

70 nSEC Access Time

DQ1

DQ2

DQ3

Vss

DQ₈

DQ₇

DQ₆

DQ₅

DQ₄

A₀

DQ₁

DQ₂

DQ₃

V_{S S}

0.22uF CAPACITOR

Top View

中文翻译

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