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AK63264BZ/3.3-30 PDF预览

AK63264BZ/3.3-30

更新时间: 2024-09-18 03:16:23
品牌 Logo 应用领域
ACCUTEK 静态存储器
页数 文件大小 规格书
2页 91K
描述
SRAM

AK63264BZ/3.3-30 数据手册

 浏览型号AK63264BZ/3.3-30的Datasheet PDF文件第2页 
Accutek  
Microcircuit  
Corporation  
AK63264BZ  
65,536 x 32 Bit CMOS/BiCMOS  
Static Random Access Memory  
DESCRIPTION  
The Accutek AK63264BZ SRAM Module consists of fast high  
performance SRAMs mounted on a low height, 64 pin SIM or ZIP  
Board. The module utilizes four 32 pin 64K x 8 SRAMs in 300 mil  
SOJ packages and four decoupling capacitors mounted on the front  
side of a printed circuit board.  
Front View  
The SRAMs used have common I/O functions and single output en-  
able functions. Also, four separate chip select (CE) connections are  
used to independently enable the four bytes. The modules can be  
supplied in a variety of access time values from 12nSEC to 35nSEC  
in CMOS or BiCMOS technology.  
32  
33  
64  
1
The Accutek module is designed to have a maximum seated height  
of 0.520 inch to provide for the lowest height off the board. Each  
conforms to JEDEC-standard sizes and pin-out configurations.  
Using two pins for module density identification, PD0 and PD1, mini-  
mizes interchangeability and design considerations when changing  
from one module size to the other in customer applications.  
· Upward compatible with 128K x 32 (AK632128), 256K x 32  
(AK632256), 512K x 32 (AK632512) and 1 Meg x 32  
(AK6321024)  
· TTL-compatible inputs and outputs  
FEATURES  
· Single 5 volt power supply - AK63264BZ  
· Single 3.3 volt power supply - AK63264BZ/3.3  
· Operating temperature range in free air, 00 to 700C  
· 65,536 x 32 bit organization  
· JEDEC Standard 64 pin ZIP format  
· Common I/O, single OE fucntions with four separate chip se-  
lects (CE)  
ELECTRICAL SPECIFICATIONS  
· Low height 0.520 inch maximum  
Timing Diagrams and basic electrical characteristics are those of  
the standard 64K x 8 SRAMs used to construct these modules.  
Accutek’s module design allows the flexibility of selecting indus-  
try-compatible 64K x 8 SRAMs from several semiconductor manu-  
facturers.  
· Presence Detect, PD0 and PD1 for identifying module density  
· Downard compatible with 32K x 32 (AK63232)  
· Fast access times from 12nSEC  
PIN NOMENCLATURE  
PIN ASSIGNMENT  
FUNCTIONAL DIAGRAM  
PIN #  
1
SYMBOL  
Vss  
PIN #  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
SYMBOL  
A2  
PIN #  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
SYMBOL  
CE4  
PIN #  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
SYMBOL  
A4  
A0 - A15  
CE1 - CE4  
DQ1 - DQ32  
OE  
Address Inputs  
Chip Enable  
Data In/Data Out  
Output Enable  
Presence Detect  
Power Supply  
Ground  
2
PD0  
PD1  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
DQ4  
DQ12  
Vcc  
A9  
CE3  
A11  
3
DQ13  
DQ5  
DQ14  
DQ6  
DQ15  
DQ7  
DQ16  
DQ8  
Vss  
NC  
A5  
4
NC  
A12  
5
OE  
Vcc  
PD0 - PD1  
Vcc  
6
Vss  
A13  
7
DQ25  
DQ17  
DQ26  
DQ18  
DQ27  
DQ19  
DQ28  
DQ20  
A3  
A6  
8
DQ21  
DQ29  
DQ22  
DQ30  
DQ23  
DQ31  
DQ24  
DQ32  
Vss  
Vss  
9
WE  
Write Enable  
No Connect  
10  
11  
12  
13  
14  
15  
16  
NC  
WE  
A0  
A15  
MODULE OPTIONS  
A7  
A14  
A1  
CE2  
CE1  
Leaded ZIP: AK63264BZ  
A8  
A10  
PD0 = Open  
PD1 = Vss  

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