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AGLE3000V2-FG484Y PDF预览

AGLE3000V2-FG484Y

更新时间: 2024-11-12 03:38:39
品牌 Logo 应用领域
美高森美 - MICROSEMI
页数 文件大小 规格书
166页 8654K
描述
Field Programmable Gate Array,

AGLE3000V2-FG484Y 数据手册

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Revision 13  
IGLOOe Low Power Flash FPGAs  
with Flash*Freeze Technology  
Bank-Selectable I/O Voltages—Up to 8 Banks per Chip  
Features and Benefits  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
Low Power  
1.2 V to 1.5 V Core Voltage Support for Low Power  
Supports Single-Voltage System Operation  
Low-Power Active FPGA Operation  
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os  
Flash*Freeze  
Technology  
Enables  
Ultra-Low  
Power  
Consumption while Maintaining FPGA Content  
Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-  
Power Flash*Freeze Mode  
High Capacity  
600 k to 3 Million System Gates  
108 to 504 kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
Programmable Output Slew Rate and Drive Strength  
Programmable Input Delay  
Schmitt Trigger Option on Single-Ended Inputs  
Weak Pull-Up/-Down  
Reprogrammable Flash Technology  
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Instant On Level 0 Support  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Single-Chip Solution  
Pin-Compatible Packages across the IGLOO e Family  
Retains Programmed Design when Powered Off  
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System  
Performance  
Clock Conditioning Circuit (CCC) and PLL  
Six CCC Blocks, Each with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
In-System Programming (ISP) and Security  
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
(AES) Decryption via JTAG (IEEE 1532–compliant)  
Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
®
Embedded Memory  
FlashLock Designed to Secure FPGA Contents  
1 kbit of FlashROM User Nonvolatile Memory  
High-Performance Routing Hierarchy  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)  
True Dual-Port SRAM (except ×18)  
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
ARM Processor Support in IGLOOe FPGAs  
Pro (Professional) I/O  
M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available  
with or without Debug  
700 Mbps DDR, LVDS-Capable I/Os  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Table 1 • IGLOOe Product Family  
IGLOOe Devices  
AGLE600  
AGLE3000  
ARM-Enabled IGLOOe Devices  
System Gates  
M1AGLE3000  
600,000  
13,824  
49  
3,000,000  
VersaTiles (D-flip-flops)  
Quiescent Current (typical) in Flash*Freeze Mode (µW)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
75,264  
137  
504  
112  
1
108  
24  
FlashROM Kbits (1,024 bits)  
Secure (AES) ISP  
1
Yes  
6
Yes  
6
CCCs with Integrated PLLs  
VersaNet Globals 1  
18  
18  
8
I/O Banks  
8
Maximum User I/Os  
270  
620  
Package Pins  
FBGA  
FG256, FG484  
FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 Handbook for more information.  
2. Six chip (main) and twelve quadrant global networks are available.  
3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology datasheet.  
December 2012  
I
© 2012 Microsemi Corporation  

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