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AGLE3000V2-FG484I PDF预览

AGLE3000V2-FG484I

更新时间： 2024-11-11 15:45:39
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
166页 8541K
描述
Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 250MHz, 75264-Cell, CMOS, PBGA484, 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484

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AGLE3000V2-FG484I 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.31
最大时钟频率：250 MHzJESD-30 代码：S-PBGA-B484
JESD-609代码：e0长度：23 mm
湿度敏感等级：3可配置逻辑块数量：75264
等效关口数量：3000000输入次数：341
逻辑单元数量：75264输出次数：341
端子数量：484最高工作温度：85 °C
最低工作温度：-40 °C组织：75264 CLBS, 3000000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA484,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：230
电源：1.2/1.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.44 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.575 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：23 mmBase Number Matches：1

AGLE3000V2-FG484I 数据手册

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Revision 13  
IGLOOe Low Power Flash FPGAs  
with Flash*Freeze Technology  
•
•
Bank-Selectable I/O Voltages—Up to 8 Banks per Chip  
Features and Benefits  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
Low Power  
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power  
Supports Single-Voltage System Operation  
Low-Power Active FPGA Operation  
•
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
Wide Range Power Supply Voltage Support per JESD8-12,  
Allowing I/Os to Operate from 1.14 V to 1.575 V  
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold-Sparing I/Os  
Flash*Freeze  
Technology  
Enables  
Ultra-Low  
Power  
Consumption while Maintaining FPGA Content  
Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-  
Power Flash*Freeze Mode  
•
•
•
High Capacity  
•
•
•
600 k to 3 Million System Gates  
108 to 504 kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
•
•
•
•
•
•
•
•
Programmable Output Slew Rate and Drive Strength  
Programmable Input Delay  
Schmitt Trigger Option on Single-Ended Inputs  
Weak Pull-Up/-Down  
Reprogrammable Flash Technology  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
•
•
•
•
Instant On Level 0 Support  
IEEE 1149.1 (JTAG) Boundary Scan Test  
®
Single-Chip Solution  
Pin-Compatible Packages across the IGLOO e Family  
Retains Programmed Design when Powered Off  
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System  
Performance  
Clock Conditioning Circuit (CCC) and PLL  
•
•
Six CCC Blocks, Each with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay Capabilities,  
and External Feedback  
In-System Programming (ISP) and Security  
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
(AES) Decryption via JTAG (IEEE 1532–compliant)  
•
Wide Input Frequency Range (1.5 MHz up to 250 MHz)  
®
Embedded Memory  
•
•
•
FlashLock Designed to Secure FPGA Contents  
1 kbit of FlashROM User Nonvolatile Memory  
High-Performance Routing Hierarchy  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)  
True Dual-Port SRAM (except ×18)  
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
•
ARM Processor Support in IGLOOe FPGAs  
•
Pro (Professional) I/O  
M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available  
with or without Debug  
•
•
700 Mbps DDR, LVDS-Capable I/Os  
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Table 1 • IGLOOe Product Family  
IGLOOe Devices  
AGLE600  
AGLE3000  
ARM-Enabled IGLOOe Devices  
System Gates  
M1AGLE3000  
600,000  
13,824  
49  
3,000,000  
VersaTiles (D-flip-flops)  
Quiescent Current (typical) in Flash*Freeze Mode (µW)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
75,264  
137  
504  
112  
1
108  
24  
FlashROM Kbits (1,024 bits)  
Secure (AES) ISP  
1
Yes  
6
Yes  
6
CCCs with Integrated PLLs  
VersaNet Globals 1  
18  
18  
8
I/O Banks  
8
Maximum User I/Os  
270  
620  
Package Pins  
FBGA  
FG256, FG484  
FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 Handbook for more information.  
2. Six chip (main) and twelve quadrant global networks are available.  
3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology datasheet.  
December 2012  
I
© 2012 Microsemi Corporation  
 
 
 
 
 
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与AGLE3000V2-FG484I相关器件

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AGLE3000V2-FG484Y MICROSEMI

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AGLE3000V2-FG484YI MICROSEMI

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 		Field Programmable Gate Array,
AGLE3000V2-FG896 ACTEL

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 		IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FG896C MICROSEMI

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 		Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA896, 31 X 31 MM, 2.23
AGLE3000V2-FG896ES ACTEL

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 		IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FG896I ACTEL

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 		IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FG896PP ACTEL

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 		IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FG896Y MICROSEMI

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 		FPGA
AGLE3000V2-FG896YI MICROSEMI

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 		FPGA
AGLE3000V2-FGG484C MICROSEMI

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 		Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23

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