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AFS250-1FGG256I PDF预览

AFS250-1FGG256I

更新时间: 2024-11-01 06:36:35
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ACTEL /
页数 文件大小 规格书
318页 10484K
描述
Actel Fusion Mixed-Signal FPGAs

AFS250-1FGG256I 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:1 MM PITCH, GREEN, FBGA-256Reach Compliance Code:compliant
风险等级:5.78最大时钟频率:350 MHz
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm湿度敏感等级:3
可配置逻辑块数量:6144等效关口数量:250000
输入次数:114逻辑单元数量:6144
输出次数:114端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
组织:6144 CLBS, 250000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):260电源:1.5,3.3 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:1.68 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:17 mm
Base Number Matches:1

AFS250-1FGG256I 数据手册

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Preliminary v1.7  
®
Actel Fusion Mixed-Signal FPGAs  
Family with Optional ARM Support  
®
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz  
Features and Benefits  
Low Power Consumption  
High-Performance Reprogrammable Flash  
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator  
• Sleep and Standby Low Power Modes  
Technology  
• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process  
• Nonvolatile, Retains Program when Powered Off  
• Live at Power-Up (LAPU) Single-Chip Solution  
• 350 MHz System Performance  
In-System Programming (ISP) and Security  
• Secure ISP with 128-Bit AES via JTAG  
®
• FlashLock to Secure FPGA Contents  
Advanced Digital I/O  
Embedded Flash Memory  
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip  
• User Flash Memory – 2 Mbits to 8 Mbits  
– Configurable 8-, 16-, or 32-Bit Datapath  
– 10 ns Access in Read-Ahead Mode  
• 1 kbit of Additional FlashROM  
• Single-Ended  
I/O  
Standards:  
LVTTL,  
LVCMOS  
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI  
LVCMOS 2.5 V / 5.0 V Input  
/ 3.3 V PCI-X, and  
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS  
– Built-In I/O Registers  
Integrated A/D Converter (ADC) and Analog I/O  
• Up to 12-Bit Resolution and up to 600 ksps  
• Internal 2.56 V or External Reference Voltage  
• ADC: Up to 30 Scalable Analog Input Channels  
• High-Voltage Input Tolerance: –10.5 V to +12 V  
• Current Monitor and Temperature Monitor Blocks  
• Up to 10 MOSFET Gate Driver Outputs  
– P- and N-Channel Power MOSFET Support  
– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths  
• ADC Accuracy is Better than 1%  
– 700 Mbps DDR Operation  
• Hot-Swappable I/Os  
• Programmable Output Slew Rate, Drive Strength, and Weak  
Pull-Up/Down Resistor  
• Pin-Compatible Packages across the Fusion Family  
SRAMs and FIFOs  
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
• True Dual-Port SRAM (except ×18)  
On-Chip Clocking Support  
• Programmable Embedded FIFO Control Logic  
• Internal 100 MHz RC Oscillator (accurate to 1%)  
• Crystal Oscillator Support (32 kHz to 20 MHz)  
• Programmable Real-Time Counter (RTC)  
• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated  
PLLs  
Soft ARM7™ Core Support in M7 and M1 Fusion Devices  
• ARM Cortex™-M1 (without debug), CoreMP7Sd (with  
debug) and CoreMP7S (without debug)  
– Phase Shift, Multiply/Divide, and Delay Capabilities  
Fusion Family  
Fusion Devices  
AFS090  
AFS250  
AFS600  
AFS1500  
CoreMP7 1  
Cortex-M1 2  
M7AFS600  
ARM-Enabled  
Fusion Devices  
M1AFS250  
M1AFS600  
M1AFS1500  
System Gates  
90,000  
2,304  
Yes  
1
250,000  
6,144  
Yes  
1
600,000  
13,824  
Yes  
2
1,500,000  
38,400  
Yes  
2
Tiles (D-flip-flops)  
Secure (AES) ISP  
PLLs  
General  
Information  
Globals  
18  
1
18  
18  
18  
Flash Memory Blocks (2 Mbits)  
Total Flash Memory Bits  
FlashROM Bits  
1
2
4
2 M  
1 k  
6
2 M  
1 k  
8
4 M  
1 k  
24  
8 M  
1 k  
60  
Memory  
RAM Blocks (4,608 bits)  
RAM kbits  
27  
5
36  
108  
10  
270  
10  
Analog Quads  
6
Analog Input Channels  
Gate Driver Outputs  
I/O Banks (+ JTAG)  
Maximum Digital I/Os  
Analog I/Os  
15  
5
18  
30  
30  
6
10  
10  
Analog and I/Os  
4
4
5
5
75  
20  
114  
24  
172  
40  
252  
40  
Notes:  
1. Refer to the CoreMP7 datasheet for more information.  
2. Refer to the Cortex-M1 product brief for more information.  
October 2008  
I
© 2008 Actel Corporation  

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