AFL120XXD Series
AFL120XXD Circuit Description
Figure I. AFL Dual Output Block Diagram
Input
Filter
Output
Filter
1
4
+ Output
DC Input
Enable 1
7
Current
Sense
Primary
Bias Supply
Output Return
-Output
8
9
Output
Filter
Sync Output
5
Share
Amplifier
Control
Share
11
Error
Amp
& Ref
Sync Input
Case
6
3
2
12 Enable 2
Trim
10
Input Return
Although incorporating several sophisticated and useful
ancilliary features, basic operation of the AFL120XXDseries
can be initiated by simply applying an input voltage to pins 1
and 2 and connecting the appropriate loads between pins 7,
8, and 9. Of course, operation of any converter with high
power density should not be attempted before secure at-
tachment to an appropriate heat dissipator. (See Thermal
Considerations, page 7)
Circuit Operation and Application Information
The AFL series of converters employ a forward switched
mode converter topology. (refer to Figure I.) Operation of
the device is initiated when a DC voltage whose magnitude
is within the specified input limits is applied between pins 1
and 2. If pins 4 and 12 are enabled (at a logical 1 or open)
the primary bias supply will begin generating a regulated
housekeeping voltage bringing the circuitry on the primary
side of the converter to life. Two power MOSFETs used to Inhibiting Converter Output
chop the DC input voltage into a high frequency square
As an alternative to application and removal of the DC volt-
wave, apply this chopped voltage to the power transformer.
As this switching is initiated, a voltage is impressed on a
second winding of the power transformer which is then
rectified and applied to the primary bias supply. When this
occurs, the input voltage is excluded from the bias voltage
generator and the primary bias voltage becomes internally
generated.
age to the input, the user can control the converter output
by providing TTL compatible, positive logic signals to either
of two enable pins (pin 4 or 12). The distinction between
these two signal ports is that enable 1 (pin 4) is referenced
to the input return (pin 2) while enable 2 (pin 12) is refer-
enced to the output return (pin 8). Thus, the user has
access to an inhibit function on either side of the isolation
barrier. Each port is internally pulled “high” so that when not
used, an open connection on both enable pins permits nor-
mal converter operation. When their use is desired, a logi-
cal “low” on either port will shut the converter down.
The switched voltage impressed on the secondary output
transformer windings is rectified and filtered to provide the
positive and negative converter output voltages. An error
amplifier on the secondary side compares the positive out-
put voltage to a precision reference and generates an error
signal proportional to the difference. This error signal is
magnetically coupled through the feedback transformer into
the control section of the converter varying the pulse width
of the square wave signal driving the MOSFETs, narrowing
the pulse width if the output voltage is too high and widening
it if it is too low. These pulse width variations provide the
necessary corrections to regulate the magnitude of output
voltage within its’ specified limits.
Figure II. Enable Input Equivalent Circuit
+5.6V
100K
1N4148
Pin 4 or
Pin 12
Disable
290K
2N3904
Because the primary portion of the circuit is coupled to the
secondary side with magnetic elements, full isolation from
input to output is maintained.
150K
Pin 2 or
Pin 8
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