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AFBR-709SMZ PDF预览

AFBR-709SMZ

更新时间: 2024-01-12 17:21:44
品牌 Logo 应用领域
安华高科 - AVAGO 以太网
页数 文件大小 规格书
19页 492K
描述
10Gb Ethernet, 850 nm, 10GBASE-SR/SW, SFP Transceiver

AFBR-709SMZ 技术参数

是否Rohs认证: 符合生命周期:Transferred
Reach Compliance Code:compliant风险等级:5.73
主体宽度:13.4 mm主体高度:8.55 mm
主体长度或直径:47.5 mm内置特性:AMPLIFIER
通信标准:GBE连接类型:LC CONNECTOR
发射极/检测器类型:LASER, PIN PHOTODIODE光纤设备类型:TRANSCEIVER
光纤类型:50/125, 62.5/125, MMF安装特点:PANEL MOUNT
最高工作温度:70 °C最低工作温度:
最大工作波长:860 nm最小工作波长:840 nm
标称工作波长:850 nm灵敏度:-11.1 dBm
子类别:Fiber Optic Transceivers最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:NOBase Number Matches:1

AFBR-709SMZ 数据手册

 浏览型号AFBR-709SMZ的Datasheet PDF文件第5页浏览型号AFBR-709SMZ的Datasheet PDF文件第6页浏览型号AFBR-709SMZ的Datasheet PDF文件第7页浏览型号AFBR-709SMZ的Datasheet PDF文件第9页浏览型号AFBR-709SMZ的Datasheet PDF文件第10页浏览型号AFBR-709SMZ的Datasheet PDF文件第11页 
Table 2. Contact Description  
Contact Symbol  
Function/Description  
Notes  
1
2
3
4
VeeT  
Transmitter Signal Ground  
Note 1  
Note 2  
Note 3  
TX_FAULT  
TX_DISABLE  
SDA  
Transmitter Fault (LVTTL-O) – High indicates a fault condition  
Transmitter Disable (LVTTL-I) – High or open disables the transmitter  
Two Wire Serial Interface Data Line (LVCMOS – I/O)  
(same as MOD-DEF2 in INF-8074)  
Note 4  
5
SCL  
Two Wire Serial Interface Clock Line (LVCMOS – I/O)  
(same as MOD-DEF1 in INF-8074)  
Note 4  
Note 5  
6
MOD_ABS  
RS0  
Module Absent (Output), connected to VeeT or VeeR in the module  
Rate Select 0 - Not used, Presents high input impedance.  
Receiver Loss of Signal (LVTTL-O)  
Rate Select 1 - Not used, Presents high input impedance.  
Receiver Signal Ground  
7
8
RX_LOS  
RS1  
Note 2  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Notes:  
VeeR  
VeeR  
RD-  
Note 1  
Note 1  
Receiver Signal Ground  
Receiver Data Out Inverted (CML-O)  
Receiver Data Out (CML-O)  
RD+  
VeeR  
VccR  
VccT  
VeeT  
TD+  
Receiver Signal Ground  
Receiver Power + 3.3 V  
Transmitter Power + 3.3 V  
Transmitter Signal Ground  
Note 1  
Note 1  
Transmitter Data In (CML-I)  
TD-  
Transmitter Data In Inverted (CML-I)  
Transmitter Signal Ground  
VeeT  
1. The module signal grounds are isolated from the module case.  
2. This is an open collector/drain output that on the host board requires a 4.7 kΩ to 10 kΩ pullup resistor to VccHost. See Figure 2.  
3. This input is internally biased high with a 4.7 kΩ to 10 kΩ pullup resistor to VccT.  
4. Two-Wire Serial interface clock and data lines require an external pullup resistor dependent on the capacitance load.  
5. This is a ground return that on the host board requires a 4.7 kΩ to 10 kΩ pullup resistor to VccHost.  
10  
11  
BOTTOM OF  
BOARD AS  
VIEWED FROM  
TOP THROUGH  
BOARD  
TOP VIEW  
OF BOARD  
TOWARD  
HOST  
1
20  
Figure 4. Module edge connector contacts  
8

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