Datasheet > ADUM6420ABRNZ3-RL

ADUM6420ABRNZ3-RL

更新时间： 2022-05-14 22:15:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
26页	533K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converter

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ADUM6420ABRNZ3-RL 数据手册

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ADuM6420A/ADuM6421A/ADuM6422A

Data Sheet

ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY

All typical specifications are at T_A= 25°C, V_DD1= V_DD2= 2.5 V. Minimum and maximum specifications apply over the entire recommended

operation range: 2.25 V ≤ V_DD1≤ 2.75 V, 2.25 V ≤ V_DD2≤ 2.75 V, and −40°C ≤ T_A≤ +125°C, unless otherwise noted. Switching specifications are

tested with C_L= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 11. Data Channel Supply Current Specifications

1 Mbps

10 Mbps

100 Mbps

Parameter

Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT

C_L= 0 pF

ADuM6420AXRNZ5/ I_DD1

4.8

1.4

4.2

2.3

3.0

8.5

2.3

8.0

4.4

6.0

4.8

2.0

4.4

2.4

3.4

9.0

3.3

8.2

5.4

6.1

6.4

6.5

6.7

6.5

6.4

11.0 mA

9.5 mA

11.5 mA

10.0 mA

ADuM6420AXRNZ3

I_DD2

ADuM6421AXRNZ5/ I_DD1

ADuM6421AXRNZ53

I_DD2

ADuM6422AXRNZ5/ I_DD1

ADuM6422AXRNZ3

9.5

I_DD2

Table 12. Switching Specifications

Parameter

Symbol Min Typ Max Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Within PWD limit

Data Rate

100

5.0

Mbps

ps/°C

Within PWD limit

50% input to 50% output

|t_PLH− t_PHL|

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

t_PHL, t_PLH

PWD

8.0

1.0

1.5

t_PSK

8.0

Between any two units at the same temperature, voltage, and

load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

1.0

816

5.0

ps p-p

Table 13. Input and Output Characteristics

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

V_OH

V_OL

V_DDx− 0.2

V_DDx− 0.5

V_DDx

V_DDx− 0.2

0.0

I_Ox¹= −20 μA, V_Ix= V_IxH

I_Ox¹= −3.2 mA, V_Ix= V_IxH

Logic Low

0.1

0.4

I_Ox¹= 20 μA, V_Ix= V_IxL

0.0

I_Ox¹= 3.2 mA, V_Ix= V_IxL

Undervoltage Lockout

Positive Going Threshold

UVLO

V_UV+

V_DD1, V_DD2, and V_DDPsupply

1.6

Negative Going Threshold V_UV−

1.5

Hysteresis

V_UVH

I_I

0.1

+0.01

μA

Input Currents per Channel

Quiescent Supply Current

ADuM6420A

−10

+10

0 V ≤ V_Ix≤ V_DDx

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

0.33

1.1

1.5

1.0

1.7

2.2

V_Ix= Logic 0

V_Ix= Logic 1

9.5

Rev. A | Page 8 of 26

1...5 6 789 10 11...26

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