Datasheet > ADUM6420ABRNZ3-RL

ADUM6420ABRNZ3-RL

更新时间： 2022-05-14 22:15:08

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
26页	533K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converter

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Data Sheet

ADuM6420A/ADuM6421A/ADuM6422A

Table 6. Switching Specifications

Parameter

Symbol Min Typ Max Unit

Test Conditions/Comments

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

Mbps

ps/°C

Within pulse width distortion (PWD) limit

Within PWD limit

50% input to 50% output

100

t_PHL, t_PLH

PWD

7.0

1.5

|t_PLH− t_PHL|

t_PSK

8.0

Between any two units at the same temperature, voltage, and

load

Channel Matching

Codirectional

Opposing Direction

Jitter

t_PSKCD

t_PSKOD

816

5.0

ps p-p

Table 7. Input and Output Characteristics

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

DC SPECIFICATIONS

Input Threshold

Logic High

V_IH

V_IL

0.7 × V_DDx

Logic Low

0.3 × V_DDx

Output Voltage

Logic High

V_OH

V_OL

V_DDx− 0.2

V_DDx− 0.5

V_DDx

V_DDx− 0.2

0.0

I_Ox¹= −20 μA, V_Ix= V_IxH

I_Ox¹= −3.2 mA, V_Ix= V_IxH

Logic Low

0.1

0.4

I_Ox¹= 20 μA, V_Ix= V_IxL

0.0

I_Ox¹= 3.2 mA, V_Ix= V_IxL

Undervoltage Lockout

Positive Going Threshold

Negative Going Threshold

Hysteresis

Input Currents per Channel

Quiescent Supply Current

ADuM6420A

UVLO

V_UV+

V_UV−

V_UVH

I_I

V_DD1, V_DD2, and V_DDPsupply

1.6

1.5

0.1

+0.01

μA

−10

+10

0 V ≤ V_Ix≤ V_DDx

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

0.37

1.2

9.5

1.2

1.9

V_Ix= Logic 0

V_Ix= Logic 1

1.5

2.5

ADuM6421A

ADuM6422A

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

0.5

0.9

7.5

3.3

1.4

1.5

V_Ix= Logic 0

V_Ix= Logic 1

6.2

I_{DD1 (Q)}

I_{DD2 (Q)}

I_{DD1 (Q)}

I_{DD2 (Q)}

0.7

0.72

5.4

1.2

1.3

9.5

9.7

V_Ix= Logic 0

V_Ix= Logic 1

5.3

Dynamic Supply Current

Input

Output

I_{DDI (D)}

I_{DDO (D)}

0.01

0.02

mA/Mbps Inputs switching, 50% duty cycle

Rev. A | Page 5 of 26

1 2 3 456 7 8...26

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