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ADUM6420ABRNZ3-RL PDF预览

ADUM6420ABRNZ3-RL

更新时间: 2022-05-14 22:15:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
26页 533K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converter

ADUM6420ABRNZ3-RL 数据手册

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Data Sheet  
ADuM6420A/ADuM6421A/ADuM6422A  
Table 10. Input and Output Characteristics  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC SPECIFICATIONS  
Input Threshold  
Logic High  
VIH  
VIL  
0.7 × VDDx  
V
V
Logic Low  
0.3 × VDDx  
Output Voltage  
Logic High  
2
VOH  
VOL  
VDDx − 0.2  
VDDx − 0.5  
VDDx  
VDDx1 – 0.2  
0.0  
V
V
V
V
IOx1 = −20 μA, VIx = VIxH  
IOx1 = −3.2 mA, VIx = VIxH  
2
3
Logic Low  
0.1  
0.4  
IOx1 = 20 μA, VIx = VIxL  
3
0.0  
IOx1 = 3.2 mA, VIx = VIxL  
Undervoltage Lockout  
Positive Going Threshold  
UVLO  
VUV+  
VDD1, VDD2, and VDDP supply  
1.6  
V
Negative Going Threshold VUV−  
1.5  
V
Hysteresis  
VUVH  
II  
0.1  
+0.01  
V
μA  
Input Currents per Channel  
Quiescent Supply Current  
ADuM6420A  
−10  
+10  
0 V ≤ VIx ≤ VDDx  
IDD1 (Q)  
IDD2 (Q)  
IDD1 (Q)  
IDD2 (Q)  
0.34  
1.1  
9.5  
1.2  
1.8  
16  
mA  
mA  
mA  
mA  
VIx = Logic 0  
VIx = Logic 0  
VIx = Logic 1  
VIx = Logic 1  
1.5  
2.4  
ADuM6421A  
ADuM6422A  
IDD1 (Q)  
IDD2 (Q)  
IDD1 (Q)  
IDD2 (Q)  
0.48  
0.8  
7.4  
1.1  
1.5  
13.5  
6.2  
mA  
mA  
mA  
mA  
VIx = Logic 0  
VIx = Logic 0  
VIx = Logic 1  
VIx = Logic 1  
3.2  
IDD1 (Q)  
IDD2 (Q)  
IDD1 (Q)  
IDD2 (Q)  
0.65  
0.7  
5.3  
1.2  
1.2  
9.5  
9.6  
mA  
mA  
mA  
mA  
VIx = Logic 0  
VIx = Logic 0  
VIx = Logic 1  
VIx = Logic 1  
5.4  
Dynamic Supply Current  
Dynamic Input  
Dynamic Output  
IDDI (D)  
IDDO (D)  
0.01  
0.01  
mA/Mbps  
mA/Mbps  
Inputs switching, 50% duty cycle  
Inputs switching, 50% duty cycle  
AC SPECIFICATIONS  
Output Rise/Fall Time  
tR/tF  
2.5  
ns  
10% to 90%  
Common-Mode Transient  
Immunity4  
|CMH|  
75  
75  
100  
kV/μs  
VIx = VDD1 or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
|CML|  
100  
kV/μs  
transient magnitude = 800 V  
1 IOX is the Channel x output current, where x is A, B, C, or D.  
2 VIXH is the input side logic high.  
3 VIXL is the input side logic low.  
4 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (VO) > 0.8 VDDx. |CML| is the maximum common-mode voltage  
slew rate that can be sustained while maintaining VO > 0.8 V. The common-mode voltage slew rates apply to both the rising and falling common-mode voltage edges.  
Rev. A | Page 7 of 26  

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