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ADuM5210BRSZ

更新时间: 2024-10-28 12:26:03
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亚德诺 - ADI 转换器
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24页 555K
描述
Dual-Channel Isolators with Integrated DC-to-DC Converters

ADuM5210BRSZ 数据手册

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Data Sheet  
ADuM5210/ADuM5211/ADuM5212  
APPLICATIONS INFORMATION  
The dc-to-dc converter section of the ADuM5210/ADuM5211/  
ADuM5212 works on principles that are common to most  
modern power supplies. It has a split controller architecture with  
isolated pulse-width modulation (PWM) feedback. VDDP power is  
supplied to an oscillating circuit that switches current into a chip-  
scale air core transformer. Power transferred to the secondary  
side is rectified and regulated to a value between 3.15 V and  
5.25 V, depending on the setpoint supplied by an external  
voltage divider (see Equation 1). The secondary (VISO) side  
controller regulates the output by creating a PWM control signal  
that is sent to the primary (VDDP) side by a dedicated iCoupler  
data channel. The PWM modulates the oscillator circuit to control  
the power being sent to the secondary side. Feedback allows for  
significantly higher power and efficiency.  
passive components to bypass the power effectively as well as  
set the output voltage and bypass the core voltage regulator (see  
Figure 24 through Figure 26).  
PDIS  
8
V
DDP  
9
GND  
P
+
10  
10µF  
0.1µF  
Figure 24. VDDP Bias and Bypass Components  
V
V
SEL  
R2  
13  
12  
11  
30k  
ISO  
GND  
ISO  
+
R1  
10kΩ  
0.1µF  
10µF  
(R1+ R2)  
VISO =1.25 V  
(1)  
R1  
Figure 25. VISO Bias and Bypass Components  
where:  
R1 is a resistor between VSEL and GNDISO  
R2 is a resistor between VSEL and VISO  
The power supply section of the ADuM5210/ADuM5211/  
ADuM5212 uses a 125 MHz oscillator frequency to efficiently  
pass power through its chip-scale transformers. Bypass capaci-  
tors are required for several operating frequencies. Noise  
suppression requires a low inductance, high frequency capacitor;  
ripple suppression and proper regulation require a large value  
bulk capacitor. These capacitors are most conveniently connected  
between Pin 9 and Pin 10 for VDDP and between Pin 11 and Pin 12  
for VISO. To suppress noise and reduce ripple, a parallel combination  
of at least two capacitors is required. The recommended capacitor  
values are 0.1 µF and 10 µF for VDD1. The smaller capacitor must  
have a low ESR; for example, use of an NPO or X5R ceramic  
capacitor is advised. Ceramic capacitors are also recommended for  
the 10 μF bulk capacitance. An additional 10 nF capacitor can be  
added in parallel if further EMI reduction  
.
.
Because the output voltage can be adjusted continuously  
there are an infinite number of operating conditions. This  
data sheet addresses three discrete operating conditions in the  
Specifications tables. Many other combinations of input and  
output voltage are possible; Figure 15 depicts the supported  
voltage combinations at room temperature. Figure 15 was  
generated by fixing the VISO load and decreasing the input  
voltage until the PWM was at 80% duty cycle. Each of the  
curves represents the minimum input voltage that is required  
for operation under this criterion. For example, if the applica-  
tion requires 30 mA of output current at 5 V, the minimum  
input voltage at VDDP is 4.25 V. Figure 15 also illustrates why  
the VDDP = 3.3 V input and VISO = 5 V configuration is not  
recommended. Even at 10 mA of output current, the PWM  
cannot maintain less than 80% duty factor, leaving no margin  
to support load or temperature variations.  
is required.  
Note that the total lead length between the ends of the low ESR  
capacitor and the input power supply pin must not exceed 2 mm.  
V
V
DD2  
DD1  
Typically, the ADuM5210/ADuM5211/ADuM5212 dissipate  
about 17% more power between room temperature and maxi-  
mum temperature; therefore, the 20% PWM margin covers  
temperature variations.  
GND  
P
GND  
ISO  
V
V
/V  
V
/V  
OA IA  
IA OA  
/V  
V /V  
OB IB  
IB OB  
ADuM5210/  
ADuM5211/  
ADuM5212  
GND  
GND  
ISO  
P
The ADuM5210/ADuM5211/ADuM5212 implement  
undervoltage lockout (UVLO) with hysteresis on the primary  
and secondary side I/O pins as well as the VDDP power input.  
This feature ensures that the converter does not go into  
oscillation due to noisy input power or slow power-on ramp rates.  
PDIS  
V
V
SEL  
V
DDP  
ISO  
GND  
GND  
ISO  
P
BYPASS < 2mm  
PCB LAYOUT  
Figure 26. Recommended PCB Layout  
The ADuM5210/ADuM5211/ADuM5212 digital isolators with  
0.15 W isoPower integrated dc-to-dc converters require no exter-  
nal interface circuitry for the logic interfaces. Power supply  
bypassing with a low ESR capacitor is required, as close to the  
chip pads as possible. The isoPower inputs require several  
In applications involving high common-mode transients, ensure  
that board coupling across the isolation barrier is minimized.  
Furthermore, design the board layout such that any coupling  
that does occur equally affects all pins on a given component side.  
Rev. 0 | Page 19 of 24  
 
 
 
 

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