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ADUC7126BSTZ126 PDF预览

ADUC7126BSTZ126

更新时间: 2024-01-29 10:11:08
品牌 Logo 应用领域
亚德诺 - ADI 时钟微控制器外围集成电路
页数 文件大小 规格书
110页 1497K
描述
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler

ADUC7126BSTZ126 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:ROHS COMPLIANT, MO-026BDD, LQFP-80针数:80
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.31
具有ADC:YES地址总线宽度:
位大小:32CPU系列:ARM7
最大时钟频率:41.78 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-PQFP-G80JESD-609代码:e3
长度:12 mm湿度敏感等级:1
I/O 线路数量:40端子数量:80
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP80,.55SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/3.3 V
认证状态:Not QualifiedRAM(字节):32768
ROM(单词):129024ROM可编程性:FLASH
座面最大高度:1.6 mm速度:41.78 MHz
子类别:Microcontrollers最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:12 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

ADUC7126BSTZ126 数据手册

 浏览型号ADUC7126BSTZ126的Datasheet PDF文件第102页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第103页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第104页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第106页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第107页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第108页 
Data Sheet  
ADuC7124/ADuC7126  
3.3V  
POWER-ON RESET OPERATION  
IOV  
LV  
DD  
An internal power-on reset (POR) is implemented on the  
ADuC7124/ADuC7126. For LVDD below 2.40 V typical, the  
internal POR holds the part in reset. As LVDD rises above 2.41 V,  
an internal timer times out for typically 128 ms before the part  
is released from reset. The user must ensure that the power  
supply, IOVDD, reaches a stable 2.7 V minimum level by this  
time. Likewise, on power-down, the internal POR holds the part  
in reset until LVDD drops below 2.40 V. Figure 69 illustrates the  
operation of the internal POR in detail.  
2.6V  
2.41V TYP  
2.41V TYP  
DD  
128ms TYP  
POR  
0.12ms TYP  
MRST  
Figure 69. Internal Power-On Reset Operation  
Rev. D | Page 105 of 110  
 
 

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