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ADUC7129BSTZ126-RL2 PDF预览

ADUC7129BSTZ126-RL2

更新时间: 2022-04-26 04:58:44
品牌 Logo 应用领域
亚德诺 - ADI 微控制器数据分配系统
页数 文件大小 规格书
92页 1808K
描述
Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC

ADUC7129BSTZ126-RL2 数据手册

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Precision Analog Microcontroller  
ARM7TDMI MCU with 12-Bit ADC and DDS DAC  
ADuC7128/ADuC7129  
In-circuit download, JTAG-based debug  
Software triggered in-circuit reprogrammability  
On-chip peripherals  
FEATURES  
Analog I/O  
Multichannel, 12-bit, 1 MSPS ADC  
2× UART, 2× I2C and SPI serial I/O  
Up to 40-pin GPIO port  
5× general-purpose timers  
Wake-up and watchdog timers (WDT)  
Power supply monitor  
16-bit PWM generator  
Quadrature encoder  
Programmable logic array (PLA)  
Power  
Up to 14 analog-to-digital converter (ADC) channels  
Fully differential and single-ended modes  
0 to VREF analog input range  
10-bit digital-to-analog converter (DAC)  
32-bit 21 MHz direct digital synthesis (DDS)  
Current-to-voltage (I/V) conversion  
Integrated second-order low-pass filter (LPF)  
DDS input to DAC  
100 Ω line driver  
On-chip voltage reference  
On-chip temperature sensor ( 3°C)  
Voltage comparator  
Microcontroller  
Specified for 3 V operation  
Active mode  
11 mA (@ 5.22 MHz)  
45 mA (@ 41.78 MHz)  
Packages and temperature range  
64-lead 9 mm × 9 mm LFCSP package, −40°C to 125°C  
64-lead LQFP, 40°C to +125°C  
80-lead LQFP, 40°C to +125°C  
Tools  
ARM7TDMI core, 16-/32-bit RISC architecture  
JTAG port supports code download and debug  
External watch crystal/clock source  
41.78 MHz PLL with 8-way programmable divider  
Optional trimmed on-chip oscillator  
Memory  
Low cost QuickStart development system  
Full third-party support  
126 kB Flash/EE memory, 8 kB SRAM  
FUNCTIONAL BLOCK DIAGRAM  
12-BIT SAR  
ADC 1MSPS  
ADC0  
T/H  
MUX  
VDAC  
OUT  
LD1TX  
LD2TX  
TEMP  
10-BIT  
DDS  
I
I/V  
SENSOR  
IOUT DAC  
LPF  
CMP0  
CMP1  
+
BAND GAP  
REFERENCE  
CMP  
OUT  
ADuC7129  
V
REF  
PWM1  
PWM2  
PWM3  
PWM4  
PWM5  
PWM6  
ARM7TDMI-BASED MCU  
WITH ADDITIONAL PERIPHERALS  
PWM  
5 GEN PURPOSE  
2 kBYTES  
TIMERS  
POR  
OSC/PLL  
PSM  
RST  
62 kBYTES 64 kBYTES 8192 BYTES  
WAKE-UP/  
RTC TIMER  
FLASH/EE FLASH/EE  
SRAM  
(2k ×  
XCLKI  
XCLKO  
XCLK  
(31k ×  
16 BITS)  
(32k ×  
16 BITS)  
32 BITS)  
S1  
S2  
QUAD  
ENCODER  
INTERRUPT  
CONTROLLER  
GPIO  
CONTROL  
2
JTAG PLA SPI  
UART0 UART1  
I C  
JTAG  
P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.3  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  
 

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