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ADUC7126BSTZ126 PDF预览

ADUC7126BSTZ126

更新时间: 2024-01-23 19:46:50
品牌 Logo 应用领域
亚德诺 - ADI 时钟微控制器外围集成电路
页数 文件大小 规格书
110页 1497K
描述
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler

ADUC7126BSTZ126 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:ROHS COMPLIANT, MO-026BDD, LQFP-80针数:80
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01风险等级:5.31
具有ADC:YES地址总线宽度:
位大小:32CPU系列:ARM7
最大时钟频率:41.78 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-PQFP-G80JESD-609代码:e3
长度:12 mm湿度敏感等级:1
I/O 线路数量:40端子数量:80
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP80,.55SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/3.3 V
认证状态:Not QualifiedRAM(字节):32768
ROM(单词):129024ROM可编程性:FLASH
座面最大高度:1.6 mm速度:41.78 MHz
子类别:Microcontrollers最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:12 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

ADUC7126BSTZ126 数据手册

 浏览型号ADUC7126BSTZ126的Datasheet PDF文件第101页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第102页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第103页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第105页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第106页浏览型号ADUC7126BSTZ126的Datasheet PDF文件第107页 
ADuC7124/ADuC7126  
Data Sheet  
For example, do not power components on the analog side (as  
seen in Figure 66b) with IOVDD because that forces return  
currents from IOVDD to flow through AGND. Avoid digital  
currents flowing under analog circuitry, which can occur if a  
noisy digital chip is placed on the left half of the board (shown  
in Figure 66c). If possible, avoid large discontinuities in the  
ground plane(s), such as those formed by a long trace on the same  
layer, because they force return signals to travel a longer path.  
In addition, make all connections to the ground plane directly,  
with little or no trace separating the pin from its via to ground.  
GROUNDING AND BOARD LAYOUT  
RECOMMENDATIONS  
As with all high resolution data converters, special attention  
must be paid to grounding and PC board layout of the  
ADuC7124/ADuC7126-based designs to achieve optimum  
performance from the ADCs and DAC.  
Although the part has separate pins for analog and digital ground  
(AGND and IOGND), the user must not tie these to two sepa-  
rate ground planes unless the two ground planes are connected  
very close to the part. This is illustrated in the simplified example  
shown in Figure 66a. In systems where digital and analog  
ground planes are connected together somewhere else (at the  
power supply of the system, for example), the planes cannot be  
reconnected near the part because a ground loop results. In these  
cases, tie all the ADuC7124/ADuC7126 AGND and IOGND  
pins to the analog ground plane, as illustrated in Figure 66b.  
In systems with only one ground plane, ensure that the digital  
and analog components are physically separated onto separate  
halves of the board so that digital return currents do not flow  
near analog circuitry (and vice versa).  
When connecting fast logic signals (rise/fall time < 5 ns) to any of  
the ADuC7124/ADuC7126 digital inputs, add a series resistor  
to each relevant line to keep rise and fall times longer than 5 ns  
at the input pins of the part. A value of 100 Ω or 200 Ω is  
usually sufficient to prevent high speed signals from coupling  
capacitively into the part and affecting the accuracy of ADC  
conversions.  
CLOCK OSCILLATOR  
The clock source for the ADuC7124/ADuC7126 can be gener-  
ated by the internal PLL or by an external clock input. To use  
the internal PLL, connect a 32.768 kHz parallel resonant crystal  
between XCLKI and XCLKO, and connect a capacitor from  
each pin to ground as shown in Figure 67. The crystal allows the  
PLL to lock correctly to give a frequency of 41.78 MHz. If no  
external crystal is present, the internal oscillator is used to give  
a typical frequency of 32.768 kHz 3ꢀ.  
The ADuC7124/ADuC7126 can then be placed between the  
digital and analog sections, as illustrated in Figure 66c.  
PLACE ANALOG  
COMPONENTS HERE  
PLACE DIGITAL  
COMPONENTS HERE  
a.  
ADuC7124/  
ADuC7126  
XCLKI  
AGND  
DGND  
12pF  
32.768kHz  
TO  
INTERNAL  
PLL  
12pF  
XCLKO  
PLACE ANALOG  
COMPONENTS  
HERE  
PLACE DIGITAL  
COMPONENTS HERE  
b.  
Figure 67. External Parallel Resonant Crystal Connections  
To use an external source clock input instead of the PLL (see  
Figure 68), Bit 1 and Bit 0 of PLLCON must be modified. The  
external clock uses P0.7 and XCLK.  
AGND  
DGND  
ADuC7124/  
ADuC7126  
XCLKO  
PLACE ANALOG  
COMPONENTS HERE  
PLACE DIGITAL  
COMPONENTS HERE  
XCLKI  
c.  
EXTERNAL  
CLOCK  
SOURCE  
TO  
FREQUENCY  
DIVIDER  
DGND  
XCLK  
Figure 68. Connecting an External Clock Source  
Figure 66. System Grounding Schemes  
Using an external clock source, the ADuC7124/ADuC7126  
specified operational clock speed range is 50 kHz to 41.78 MHz  
1ꢀ, which ensures correct operation of the analog peripherals  
and Flash/EE.  
In all of these scenarios, and in more complicated real-life  
applications, the users should pay particular attention to the  
flow of current from the supplies and back to ground. Make  
sure the return paths for all currents are as close as possible to  
the paths the currents took to reach their destinations.  
Rev. D | Page 104 of 110  
 
 
 
 
 

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