Datasheet > ADSP-SC571CSWZ-3

ADSP-SC571CSWZ-3

更新时间： 2024-11-01 02:40:27

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
142页	3845K
描述
SHARC Dual-Core DSP with ARM Cortex-A5

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ADSP-SC571CSWZ-3 数据手册

SHARC+ Dual-Core

DSP with ARM Cortex-A5

ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573

17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP,

RoHS compliant

SYSTEM FEATURES

Dual-enhanced SHARC+ high performance floating-point

cores

Low system power across automotive temperature range

MEMORY

Up to 500 MHz per SHARC+ core

Up to 3 Mb (384 kB) L1 SRAM memory per core with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

Large on-chip L2 SRAM with ECC protection, up to 1 MB

One L3 interface optimized for low system power, providing

16-bit interface to DDR3 (supporting 1.5 V capable DDR3L

devices), DDR2, or LPDDR1 SDRAM devices

Byte, short word, word, long word addressed

ARM Cortex-A5 core

500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle

32 kB L1 instruction cache with parity/32 kB L1 data cache

with parity

256 kB L2 cache with parity

Powerful DMA system

On-chip memory protection

Integrated safety features

ADDITIONAL FEATURES

Security and Protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Support for ARM TrustZone

Accelerators

FIR, IIR offload engines

Qualified for automotive applications

CORE 0

CORE 1

CORE 2

PERIPHERALS

SYSTEM CONTROL

SIGNAL ROUTING UNIT (SRU)

2× PRECISION CLOCK

SECURITY AND PROTECTION

SYSTEM PROTECTION (SPU)

GENERATORS

1x DAI

1x PIN

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

ASRC

FULL SPORT

0-3

4× PAIRS

BUFFER

L1 CACHE (PARITY)

32 kB L1 I-CACHE

32 kB L1 D-CACHE

FAULT MANAGEMENT

1× S/PDIF Rx/Tx

3× I²C

L1 SRAM (PARITY)

ARM TrustZone SECURITY

3 Mb (384 kB)

SRAM/CACHE

3 Mb (384 kB)

SRAM/CACHE

DUAL CRC

L2 CACHE

256 kB (PARITY)

2× LINK PORTS

2× SPI + 1× QUAD SPI

3× UARTs

WATCHDOGS

OTP MEMORY

THERMAL MONITOR UNIT (TMU)

1× EPPI

PROGRAM FLOW

SYSTEM CROSSBAR AND DMA SUBSYSTEM

8× TIMERS + 1× COUNTER

SYS EVENT CORE 0 (GIC)

ADC CONTROL MODULE

(ACM)

SYS EVENT CORES 1-2 (SEC)

TRIGGER ROUTING (TRU)

92–64

2× CAN2.0

SD/SDIO/eMMC

L3 MEMORY

INTERFACE

SYSTEM

L2 MEMORY

SYSTEM

ACCELERATION

DSP FUNCTIONS

(FIR, IIR)

CLOCK, RESET, AND POWER

CLOCK GENERATION (CGU)

MLB 3-PIN

1× EMAC

DDR3

DDR2

LPDDR1

SRAM

(ECC)

8 Mb (1 MB)

CLOCK DISTRIBUTION

UNIT (CDU)

8x SHARC FLAGS

ENCRYPTION/DECRYPTION

RESET CONTROL (RCU)

1 USB 2.0 HS

MLB 6-PIN

POWER MANAGEMENT (DPM)

DATA

HADC (8 CHAN, 12-BIT)

DEBUG UNIT

8–4

ARM CoreSight

WATCHPOINTS (SWU)

Figure 1. Processor Block Diagram

SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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与ADSP-SC571CSWZ-3相关器件

型号	品牌	获取价格	描述	数据表
ADSP-SC571CSWZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC571CSWZ-5	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC571KSWZ-3	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC571KSWZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC571KSWZ-5	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC572	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC572BBCZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC572BBCZ-42	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC572CBCZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-SC572CBCZ-42	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5

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