a
DSP Microcomputers
ADSP-21msp58/59
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
38 ns Instruction Cycle Tim e (26 MIPS) from 13.00 MHz
Crystal
POWERDOWN
CONTROL
LOGIC
MEMORY
ADSP-21msp58/59
ADSP-21msp59
ADSP-2100 Fam ily Code and Function Com patible w ith
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
2K ؋
24 Words of On-Chip Program Mem ory RAM
2K ؋
16 Words of On-Chip Data Mem ory RAM
4K ؋
24 Words of On-Chip Program Mem ory ROM
(ADSP-21m sp59 Only)
FLAG
DATA
PROGRAM
MEMORY
4K x 24
PROGRAM
MEMORY
2K x 24
DATA
MEMORY
2K x 16
ADDRESS
PROGRAM
SEQUENCER
GENERATORS
ANALOG
INTERFACE
(ROM)
DAG 1 DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
8-Bit Parallel Host Interface Port
Analog Interface Provides:
16-Bit Sigm a-Delta ADC and DAC
ARITHMETIC UNITS
ALU SHIFTER
TIMER
MAC
HOST
INTERFACE
PORT
SERIAL PORTS
SPORT 1
Program m able Gain Stages
On-Chip Anti-Aliasing & Anti-Im aging Filters
8 kHz Sam pling Frequency
SPORT 0
ADSP-2100 BASE
ARCHITECTURE
65 dB ADC, SNR and THD
GENERAL D ESCRIP TIO N
72 dB DAC, SNR and THD
T he ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-
cessors (MSProcessor® DSPs) are fully integrated, single-chip
DSPs complete with a high performance analog front end. T he
ADSP-21msp58/59 Family is optimized for voice band applica-
tions such as Speech Compression, Speech Processing, Speech
Recognition, T ext-to Speech, and Speech-to-T ext conversion.
425 m W Typical Pow er Dissipation @ 5.0 V @ 38 ns
<1 m W Pow erdow n Mode w ith 100 Cycle Recovery
Dual Purpose Program Mem ory for Both Instruction
and Data Storage
Independent ALU, Multiplier/ Accum ulator, and Barrel
Shifter Com putational Units
Tw o Independent Data Address Generators
Pow erful Program Sequencer Provides:
Zero Overhead Looping
T he ADSP-21msp58/59 combines the ADSP-2100 base archi-
tecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
Conditional Instruction Execution
Tw o Double-Buffered Serial Ports w ith Com panding
Hardw are, One Serial Port (SPORT0) has Autom atic
Data Buffering
Program m able 16-Bit Interval Tim er w ith Prescaler
Program m able Wait State Generation
Autom atic Booting of Internal Program Mem ory from
Byte-Wide External Mem ory, e.g., EPROM, or
Through Host Interface Port
T he ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. T he ADSP-
21msp59 provides an additional 4K words (24-bit) of program
ROM. T he ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. T he
ADSP-21msp58/59 is available in a 100-pin T QFP package
(thin quad flat package).
Stand-Alone ROM Execution (ADSP-21m sp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
Multifunction Instructions
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
Three Edge- or Level-Sensitive External Interrupts
Low Pow er Dissipation in Standby Mode
100-Lead TQFP
MSProcessor is a registered trademark of Analog Devices, Inc.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
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