ADSP-2100 Family
DSP Microcomputers
a
ADSP-21xx
FUNCTIO NAL BLO CK D IAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors w ith
On-Chip Mem ory
Enhanced Harvard Architecture for Three-Bus
Perform ance: Instruction Bus & Dual Data Buses
Independent Com putation Units: ALU, Multiplier/
Accum ulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Mem ory RAM or ROM
& Data Mem ory RAM
MEMORY
FLAGS
DATA ADDRESS
GENERATORS
(ADSP-2111)
PROGRAM
SEQUENCER
DATA
MEMORY
PROGRAM
MEMORY
DAG 1
DAG 2
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
Integrated I/ O Peripherals: Serial Ports, Tim er,
Host Interface Port (ADSP-2111 Only)
HOST
INTERFACE
PORT
SERIAL PORTS
SPORT 0 SPORT 1
ARITHMETIC UNITS
MAC
TIMER
SHIFTER
ALU
FEATURES
(ADSP-2111)
25 MIPS, 40 ns Maxim um Instruction Rate
Separate On-Chip Buses for Program and Data Mem ory
Program Mem ory Stores Both Instructions and Data
(Three-Bus Perform ance)
Dual Data Address Generators w ith Modulo and
Bit-Reverse Addressing
ADSP-2100 CORE
T his data sheet describes the following ADSP-2100 Family
processors:
ADSP-2101
Efficient Program Sequencing w ith Zero-Overhead
Looping: Single-Cycle Loop Setup
ADSP-2103
ADSP-2105
ADSP-2111
ADSP-2115
3.3 V Version of ADSP-2101
Low Cost DSP
DSP with Host Interface Port
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory (e.g., EPROM )
Double-Buffered Serial Ports w ith Com panding Hardw are,
Autom atic Data Buffering, and Multichannel Operation
ADSP-2111 Host Interface Port Provides Easy Interface
to 68000, 80C51, ADSP-21xx, Etc.
ADSP-2161/62/63/64 Custom ROM-programmed DSPs
T he following ADSP-2100 Family processors are not included
in this data sheet:
Autom atic Booting of ADSP-2111 Program Mem ory
Through Host Interface Port
Three Edge- or Level-Sensitive Interrupts
Low Pow er IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available
ADSP-2100A
DSP Microprocessor
ADSP-2165/66
ROM-programmed ADSP-216x processors
with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)
ADSP-21msp5x
ADSP-2171
Mixed-Signal DSP Processors with
integrated on-chip A/D and D/A plus
powerdown
GENERAL D ESCRIP TIO N
T he ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. T he
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture—computation
units, data address generators, and program sequencer—with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.
Speed and feature enhanced ADSP-2100
Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking
ADSP-2181
ADSP-21xx processor with ADSP-2171
features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.
Refer to the individual data sheet of each of these processors for
further information.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
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