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ADSP-21992YBC

更新时间: 2024-11-11 03:13:15
品牌 Logo 应用领域
亚德诺 - ADI 控制器
页数 文件大小 规格书
60页 2028K
描述
Mixed-Signal DSP Controller with CAN

ADSP-21992YBC 数据手册

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Mixed-Signal DSP Controller with CAN  
ADSP-21992  
Dual 16-bit auxiliary PWM outputs  
FEATURES  
16 general-purpose flag I/O pins  
ADSP-2199x, 16-bit, fixed-point DSP core with up to 160  
MIPS sustained performance  
48K words of on-chip RAM, as 32K words on-chip 24-bit pro-  
gram RAM, and 16K words on-chip, 16-bit data RAM  
External memory interface  
Dedicated memory DMA controller for data/instruction  
transfer between internal/external memory  
Programmable PLL and flexible clock generation circuitry  
enables full-speed operation from low speed  
input clocks  
3 programmable 32-bit interval timers  
SPI communications port with master or slave operation  
Synchronous serial communications port (SPORT) capable of  
software UART emulation  
Controller area network (CAN) module, fully compliant with  
V2.0B standard  
Integrated watchdog timer  
Dedicated peripheral interrupt controller with software  
priority control  
Multiple boot modes  
IEEE JTAG Standard 1149.1 test access port supports on-chip  
emulation and system debugging  
Precision 1.0 V voltage reference  
Integrated power-on-reset (POR) generator  
Flexible power management with selectable power-down  
and idle modes  
2.5 V internal operation with 3.3 V I/O  
Operating temperature ranges of –40ЊC to +85ЊC and –40ЊC  
to +125ЊC  
8-channel, 14-bit analog-to-digital converter system, with up  
to 20 MSPS sampling rate (at 160 MHz core clock rate)  
3-phase 16-bit center based PWM generation unit with 12.5  
ns resolution at 160 MHz core clock (CCLK) rate  
Dedicated 32-bit encoder interface unit with companion  
encoder event timer  
CLOCK  
GENERATOR/PLL  
16K ϫ 16  
DM RAM  
4K ϫ 24  
PM ROM  
32K ϫ 24  
PM RAM  
JTAG  
TEST AND  
EMULATION  
ADSP-219x  
DSP CORE  
ADDRESS  
EXTERNAL  
MEMORY  
INTERFACE  
(EMI)  
DATA  
I/O  
BUS  
PM ADDRESS/DATA  
DM ADDRESS/DATA  
CONTROL  
I/O REGISTERS  
CONTROLLER AREA  
NETWORK (CAN)  
MEMORY DMA  
CONTROLLER  
SPI  
SPORT  
PWM  
GENERATION  
ENCODER  
INTERFACE  
UNIT  
(AND EET)  
TIMER 0  
ADC  
CONTROL  
PIPELINE  
FLASH ADC  
INTERRUPT  
CONTROLLER  
AUXILIARY  
PWM  
UNIT  
WATCHDOG  
TIMER  
TIMER 1  
TIMER 2  
FLAG  
I/O  
UNIT  
(ICNTL)  
POR  
VREF  
Figure 1. Functional Block Diagram  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.3113  
www.analog.com  
©2007 Analog Devices, Inc. All rights reserved.  

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