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ADSP-2186L1111

更新时间: 2024-11-26 22:24:03
品牌 Logo 应用领域
亚德诺 - ADI 电脑
页数 文件大小 规格书
36页 269K
描述
DSP Microcomputer

ADSP-2186L1111 数据手册

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a
DSP Microcomputer  
ADSP-2186L  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
Performance  
25 ns Instruction Cycle Time 40 MIPS Sustained  
Performance  
Single-Cycle Instruction Execution  
Single-Cycle Context Switch  
3-Bus Architecture Allows Dual Operand Fetches in  
Every Instruction Cycle  
POWER-DOWN  
CONTROL  
FULL MEMORY  
MODE  
MEMORY  
PROGRAMMABLE  
DATA ADDRESS  
GENERATORS  
I/O  
EXTERNAL  
ADDRESS  
BUS  
8K 
؋
 24  
PROGRAM  
MEMORY  
8K 
؋
 16  
DATA  
MEMORY  
PROGRAM  
SEQUENCER  
AND  
FLAGS  
DAG 2  
DAG 1  
EXTERNAL  
DATA  
BUS  
PROGRAM MEMORY ADDRESS  
DATA MEMORY ADDRESS  
Multifunction Instructions  
BYTE DMA  
CONTROLLER  
Power-Down Mode Featuring Low CMOS Standby  
Power Dissipation with 400 Cycle Recovery from  
Power-Down Condition  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
OR  
EXTERNAL  
DATA  
BUS  
Low Power Dissipation in Idle Mode  
ARITHMETIC UNITS  
SERIAL PORTS  
SPORT 0 SPORT 1  
TIMER  
INTERNAL  
DMA  
PORT  
Integration  
ALU MAC SHIFTER  
ADSP-2100 Family Code Compatible, with Instruction  
Set Extensions  
ADSP-2100 BASE  
ARCHITECTURE  
HOST MODE  
40K Bytes of On-Chip RAM, Configured as  
8K Words On-Chip Program Memory RAM and  
8K Words On-Chip Data Memory RAM  
Dual Purpose Program Memory for Both Instruction  
and Data Storage  
Independent ALU, Multiplier/Accumulator and Barrel  
Shifter Computational Units  
13 Programmable Flag Pins Provide Flexible System  
Signaling  
UART Emulation through Software SPORT Reconfiguration  
ICE-Port™ Emulator Interface Supports Debugging  
in Final Systems  
Two Independent Data Address Generators  
Powerful Program Sequencer Provides  
Zero Overhead Looping Conditional Instruction  
Execution  
Programmable 16-Bit Interval Timer with Prescaler  
100-Lead LQFP and 144-Ball Mini-BGA  
GENERAL DESCRIPTION  
The ADSP-2186L is a single-chip microcomputer optimized for  
digital signal processing (DSP) and other high speed numeric  
processing applications.  
The ADSP-2186L combines the ADSP-2100 family base archi-  
tecture (three computational units, data address generators  
and a program sequencer) with two serial ports, a 16-bit inter-  
nal DMA port, a byte DMA port, a programmable timer, Flag  
I/O, extensive interrupt capabilities and on-chip program and  
data memory.  
System Interface  
16-Bit Internal DMA Port for High Speed Access to  
On-Chip Memory (Mode Selectable)  
4 MByte Byte Memory Interface for Storage of Data  
Tables and Program Overlays  
8-Bit DMA to Byte Memory for Transparent Program  
and Data Memory Transfers (Mode Selectable)  
I/O Memory Interface with 2048 Locations Supports  
Parallel Peripherals (Mode Selectable)  
Programmable Memory Strobe and Separate I/O Memory  
Space Permits “Glueless” System Design  
(Mode Selectable)  
Programmable Wait State Generation  
Two Double-Buffered Serial Ports with Companding  
Hardware and Automatic Data Buffering  
Automatic Booting of On-Chip Program Memory from  
Byte-Wide External Memory, e.g., EPROM, or  
Through Internal DMA Port  
The ADSP-2186L integrates 40K bytes of on-chip memory  
configured as 8K words (24-bit) of program RAM and 8K  
words (16-bit) of data RAM. Power-down circuitry is also pro-  
vided to meet the low power needs of battery operated portable  
equipment. The ADSP-2186L is available in a 100-lead LQFP  
and 144-ball mini-BGA packages.  
In addition, the ADSP-2186L supports new instructions, which  
include bit manipulations—bit set, bit clear, bit toggle, bit test—  
new ALU constants, new multiplication instruction (x squared),  
biased rounding, result free ALU operations, I/O memory trans-  
fers and global interrupt masking for increased flexibility.  
Fabricated in a high speed, double metal, low power, CMOS  
process, the ADSP-2186L operates with a 25 ns instruction cycle  
time. Every instruction can execute in a single processor cycle.  
Six External Interrupts  
The ADSP-21xx family DSPs contain a shadow bank register  
that is useful for single cycle context switching of the processor.  
ICE-Port is a trademark of Analog Devices, Inc.  
All other trademarks are the property of their respective holders.  
REV. B  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  

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