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ADSP-2186LBST-1602 PDF预览

ADSP-2186LBST-1602

更新时间: 2024-11-24 12:47:59
品牌 Logo 应用领域
亚德诺 - ADI 电脑
页数 文件大小 规格书
48页 630K
描述
DSP Microcomputer

ADSP-2186LBST-1602 数据手册

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DSP Microcomputer  
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L  
SYSTEM INTERFACE FEATURES  
PERFORMANCE FEATURES  
Up to 19 ns instruction cycle time, 52 MIPS sustained  
performance  
16-bit internal DMA port for high-speed access to on-chip  
memory (mode selectable)  
Single-cycle instruction execution  
Single-cycle context switch  
4M-byte memory interface for storage of data tables and pro-  
gram overlays (mode selectable)  
8-bit DMA to byte memory for transparent program and data  
memory transfers (mode selectable)  
3-bus architecture allows dual operand fetches in every  
instruction cycle  
Programmable memory strobe and separate I/O memory  
space permits “glueless” system design  
Programmable wait state generation  
2 double-buffered serial ports with companding hardware  
and automatic data buffering  
Multifunction instructions  
Power-down mode featuring low CMOS standby power dissi-  
pation with 400 CLKIN cycle recovery from power-down  
condition  
Low power dissipation in idle mode  
Automatic booting of on-chip program memory from byte-  
wide external memory, for example, EPROM, or through  
internal DMA Port  
INTEGRATION FEATURES  
ADSP-2100 family code compatible (easy to use algebraic  
syntax), with instruction set extensions  
Up to 160K bytes of on-chip RAM, configured  
Up to 32K words program memory RAM  
Up to 32K words data memory RAM  
6 external interrupts  
13 programmable flag pins provide flexible system signaling  
UART emulation through software SPORT reconfiguration  
ICE-Port emulator interface supports debugging in final  
systems  
Dual-purpose program memory for both instruction and  
data storage  
Independent ALU, multiplier/accumulator, and barrel shifter  
computational units  
2 independent data address generators  
Powerful program sequencer provides zero overhead loop-  
ing conditional instruction execution  
Programmable 16-bit interval timer with prescaler  
100-lead LQFP and 144-ball BGA  
POWER-DOWN  
CONTROL  
FULL MEMORY MODE  
PROGRAMMABLE  
MEMORY  
PROGRAM  
EXTERNAL  
ADDRESS  
BUS  
DATA  
MEMORY  
UP TO  
DATA ADDRESS  
GENERATORS  
I/O  
MEMORY  
UP TO  
32K 
؋
 24-BIT  
PROGRAM  
SEQUENCER  
AND  
FLAGS  
DAG1 DAG2  
32K 
؋
 16-BIT  
EXTERNAL  
DATA  
BUS  
PROGRAM MEMORY ADDRESS  
DATA MEMORY ADDRESS  
BYTE DMA  
CONTROLLER  
PROGRAM MEMORY DATA  
DATA MEMORY DATA  
OR  
EXTERNAL  
DATA  
BUS  
ARITHMETIC UNITS  
SERIAL PORTS  
TIMER  
INTERNAL  
DMA  
PORT  
ALU  
MAC  
SHIFTER  
SPORT0  
SPORT1  
ADSP-2100 BASE  
ARCHITECTURE  
HOST MODE  
Figure 1. Functional Block Diagram  
ICE-Port is a trademark of Analog Devices, Inc.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  

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