ADSP-21261

更新时间： 2024-01-03 14:16:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	1232K
描述
SHARC Embedded Processor

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技术参数
数据手册

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ADSP-21261 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	MO-205-AE, CSP, BGA-136	针数：	136
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.55
地址总线宽度：	16	桶式移位器：	YES
位大小：	32	边界扫描：	YES
最大时钟频率：	50 MHz	外部数据总线宽度：	16
格式：	FLOATING POINT	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PBGA-B136	JESD-609代码：	e0
长度：	12 mm	低功率模式：	NO
端子数量：	136	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA136,14X14,32
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.2,3.3 V
认证状态：	Not Qualified	RAM（字数）：	32768
座面最大高度：	1.7 mm	子类别：	Digital Signal Processors
最大压摆率：	375 mA	最大供电电压：	1.26 V
最小供电电压：	1.14 V	标称供电电压：	1.2 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	12 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-21261 数据手册

ADSP-21261

complexity, this capability can have increasing significance on

the designer’s development schedule, increasing productivity.

Statistical profiling enables the programmer to nonintrusively

poll the processor as it is running the program. This feature,

unique to VisualDSP++, enables the software developer to pas-

sively gather important code execution metrics without

interrupting the real-time characteristics of the program. Essen-

tially, the developer can identify bottlenecks in software quickly

and efficiently. By using the profiler, the programmer can focus

on those areas in the program that impact performance and take

corrective action.

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. It also is used for downloading components from the

Web, dropping them into the application, and publishing com-

ponent archives from within VisualDSP++. VCSE supports

component implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with a drag of

the mouse, and examine runtime stack and heap usage. The

expert linker is fully compatible with existing linker definition

file (LDF), allowing the developer to move between the graphi-

cal and textual environments.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third-

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tools’

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

Rev. 0

Page 9 of 44 | March 2006

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与ADSP-21261相关器件

型号	品牌	描述	获取价格	数据表
ADSP-21261SKBC-150	ADI	SHARC Embedded Processor	获取价格
ADSP-21261SKBCZ150	ADI	SHARC Embedded Processor	获取价格
ADSP-21261SKBCZ-X	ADI	暂无描述	获取价格
ADSP-21261SKSTZ150	ADI	SHARC Embedded Processor	获取价格
ADSP-21261SKSTZ-X	ADI	暂无描述	获取价格
ADSP-21262	ADI	SHARC Processor	获取价格

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