ADSP-21160M
FEATURES (CONTINUED)
GENERAL DESCRIPTION
The ADSP-21160M SHARC DSP is the first processor in
a new family featuring Analog Devices’ Super Harvard
Architecture. Easing portability, the ADSP-21160M is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (Single Instruction,
Single Data) mode. To take advantage of the processor’s
SIMD(Single Instruction, Multiple Data) capability, some
code changes are needed. Like other SHARCs, the
ADSP-21160M is a 32-bit processor that is optimized for
high performance DSP applications. The ADSP-21160M
includes an80 MHz core, a dual-portedon-chipSRAM, an
integratedI/Oprocessor withmultiprocessing support, and
multiple internal buses to eliminate I/O bottlenecks.
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bit On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160M Internal Memory and External
Memory, External Peripherals, Host Processor, Serial
Ports, or Link Ports
The ADSP-21160M introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160M can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160M has a 12.5 ns instruc-
tion cycle time. With its SIMD computational hardware
running at 80 MHz, the ADSP-21160M can perform 480
million math operations per second.
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
560M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
Table 1 shows performance benchmarks for the
ADSP-21160M.
Table 1. ADSP-21160M Benchmarks
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ms plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 40M Bit/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Benchmark Algorithm
Speed
1024 Point Complex FFT(Radix 4, with 115 µs
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
Matrix Multiply (pipelined)
Divide (y/x)
6.25 ns
25 ns
56.25 ns
100 ns
37.5 ns
56.25 ns
560M Bytes/s
Inverse Square Root
DMA Transfer Rate
Thesebenchmarksprovidesingle-channel extrapolationsof
measured dual-channel processing performance. For more
informationonbenchmarkingandoptimizingDSPcodefor
single- and dual-channel processing, see Analog Devices’s
website.
Up to 40 MHz Operation
The ADSP-21160M continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance32-bitDSPcorewithintegrated,on-chip
system features. These features include a 4M bit dual
ported SRAM memory, host processor interface, I/O
processor that supports 14 DMAchannels, twoserial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
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