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ADSP-21160MKB-80

更新时间： 2024-02-18 23:25:08
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器电脑时钟
页数 文件大小 规格书
53页 695K
描述
DSP Microcomputer

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ADSP-21160MKB-80 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA,针数：400
Reach Compliance Code：unknown风险等级：5.74
Is Samacsys：N地址总线宽度：32
桶式移位器：YES边界扫描：YES
最大时钟频率：80 MHz外部数据总线宽度：64
格式：FLOATING POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B400JESD-609代码：e0
长度：27 mm低功率模式：YES
湿度敏感等级：3端子数量：400
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225认证状态：COMMERCIAL
座面最大高度：2.49 mm最大供电电压：2.63 V
最小供电电压：2.37 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：TIN LEAD SILVER
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：27 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

ADSP-21160MKB-80 数据手册

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ADSP-21160M  
ADSP-21160M Family Core Architecture  
The functional block diagram on page 1 shows a block  
diagram of the ADSP-21160M, illustrating the following  
architectural features:  
The ADSP-21160M includes the following archi-  
tectural features of the ADSP-2116x family core. The  
ADSP-21160M is code compatible at the assembly level  
with the ADSP-21060, ADSP-21061, and ADSP-21062.  
• Two processing elements, each made up of an ALU, Mul-  
tiplier, Shifter, and Data Register File  
• Data Address Generators (DAG1, DAG2)  
• Program sequencer with instruction cache  
SIMD Computational Engine  
The ADSP-21160M contains two computational process-  
ing elements that operate as a Single Instruction Multiple  
Data (SIMD) engine. The processing elements are referred  
to as PEX and PEY, and each contains an ALU, multiplier,  
shifter, and register file. PEX is always active, and PEY may  
be enabled by setting the PEYEN mode bit in the MODE1  
register. When this mode is enabled, the same instruction  
isexecutedinbothprocessingelements,buteachprocessing  
element operates on different data. This architecture is  
efficient at executing math-intensive DSP algorithms.  
• PMandDMbuses capable of supporting four 32-bit data  
transfers between memory and the core every core  
processor cycle  
• Interval timer  
• On-Chip SRAM (4 Mbit)  
• External port that supports:  
• Interfacing to off-chip memory peripherals  
• Glueless multiprocessing support for six  
ADSP-21160M SHARCs  
Entering SIMD mode also has an effect on the way data is  
transferred between memory and the processing elements.  
When in SIMD mode, twice the data bandwidth is required  
to sustain computational operation in the processing  
elements. Because of this requirement, entering SIMD  
mode also doubles the bandwidth between memory and the  
processingelements. Whenusingthe DAGs totransfer data  
in SIMD mode, two data values are transferred with each  
access of memory or the register file.  
• Host port  
• DMA controller  
• Serial ports and link ports  
• JTAG test access port  
Figure 1 shows a typical single-processor system. A multi-  
processing system appears in Figure 4.  
Independent, Parallel Computation Units  
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Within each processing element is a set of computational  
units. The computational units consist of an arith-  
metic/logic unit (ALU), multiplier, and shifter. These units  
perform single-cycle instructions. The three units within  
each processing element are arranged in parallel, maximiz-  
ing computational throughput. Single multifunction  
instructions execute parallel ALU and multiplier opera-  
tions. In SIMD mode, the parallel ALU and multiplier  
operations occur in both processing elements. These com-  
putation units support IEEE 32-bit single-precision  
floating-point, 40-bit extended precision floating-point,  
and 32-bit fixed-point data formats.  
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Data Register File  
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A general-purpose data register file is contained in each  
processing element. The register files transfer data between  
the computation units and the data buses, and store inter-  
mediate results. These 10-port, 32-register (16 primary, 16  
secondary) register files, combined with the ADSP-2116x  
enhanced Harvard architecture, allow unconstrained data  
flow between computation units and internal memory. The  
registers in PEX are referred to as R0–R15 and in PEY  
as S0–S15.  
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Figure 1. Single-Processor System  
Single-Cycle Fetch of Instruction and Four Operands  
The ADSP-21160M features an enhanced Harvard archi-  
tecture in which the data memory (DM) bus transfers data,  
and the program memory (PM) bus transfers both instruc-  
tionsanddata(seethefunctional blockdiagramon page 1).  
REV. 0  
–3–  
1234567...53

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ADSP-21160MKB-80 替代型号

型号 品牌 替代类型 描述 数据表
ADSP-21160MKBZ-80 ADI

完全替代

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