Datasheet > ADS62C15_10

ADS62C15_10

更新时间： 2024-02-10 08:29:44

品牌	Logo	应用领域
德州仪器 - TI		双倍数据速率
页数	文件大小	规格书
64页	1549K
描述
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

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ADS62C15_10 数据手册

ADS62C15

www.ti.com ....................................................................................................................................................... SLAS577D–JANUARY 2008–REVISED JULY 2009

Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs

FEATURES

•

Maximum Sample Rate: 125 MSPS

11-Bit Resolution With No Missing Codes

82 dBc SFDR at Fin = 117 MHz

•

Supports Sine, LVPECL, LVDS and LVCMOS

Clocks and Amplitude Down to 400 mV_PP

•

Clock Duty Cycle Stabilizer

Internal Reference; Also Supports External

Reference

67 dBFS SNR at Fin = 117 MHz

77.5 dBFS SNR at Fin = 117 MHz, 20MHz

bandwidth using SNRBoost technology

•

64-QFN Package (9mm × 9mm)

•

92 dB Crosstalk

APPLICATIONS

Parallel CMOS and DDR LVDS Output Options

•

Wireless Communications Infrastructure

Software Defined Radio

Power Amplifier Linearization

802.16d/e

Medical Imaging

Radar Systems

3.5 dB Coarse Gain and Programmable Fine

Gain up to 6 dB for SNR/SFDR Trade-Off

•

Digital Processing Block With:

–

Offset Correction

Fine Gain Correction, in Steps of 0.05 dB

Decimation by 2/4/8

Test and Measurement Instrumentation

Built-in and Custom Programmable 24-Tap

Low/High /Band Pass Filters

DESCRIPTION

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines

high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold

and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse

and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary SNRBoost technology that can be used to overcome SNR limitation due to

quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of

several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps

of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing

block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes

internal references while traditional reference pins and associated decoupling capacitors have been eliminated.

The device can also be driven with an external reference. The device is specified over the industrial temperature

range (–40°C to 85°C).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...64

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与ADS62C15_10相关器件

型号	品牌	获取价格	描述	数据表
ADS62C15IRGC25	TI	获取价格	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62C15IRGCR	TI	获取价格	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62C15IRGCRG4	TI	获取价格	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62C15IRGCT	TI	获取价格	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62C15IRGCTG4	TI	获取价格	Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62C17	TI	获取价格	Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
ADS62C17_1	TI	获取价格	Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
ADS62C17IRGC25	TI	获取价格	Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
ADS62C17IRGCR	TI	获取价格	Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
ADS62C17IRGCT	TI	获取价格	Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

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