750 MHz to 1160 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6601
The PLL reference input can support input frequencies from
12 MHz to 160 MHz. The PFD output controls a charge pump
whose output drives an off-chip loop filter.
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 300 MHz to 2500 MHz
Internal LO frequency range: 750 MHz to 1160 MHz
Input P1dB: 14.2 dBm
Input IP3: 30.0 dBm
IIP3 optimization via external pin
SSB noise figure
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a Σ-Δ modulator (SDM). The modulus of the SDM
can be programmed from 1 to 2047.
IP3SET pin open: 13.0 dB
IP3SET pin at 3.3 V: 13.8 dB
The active mixer converts the single-ended 50 Ω RF input to
a 200 ꢀ differential IF output. The IF output can operate up
to 500 MHz.
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
The ADRF6601 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
APPLICATIONS
Table 1.
Cellular base stations
Internal
LO Range
3 dB RF Input
Balun Range
1 dB RF Input
Balun Range
GENERAL DESCRIPTION
Part No.
ADRF6601
750 MHz to
1160 MHz
1550 MHz to 1000 MHz to
2150 MHz 3100 MHz
2100 MHz to 1100 MHz to
300 MHz to
2500 MHz
450 MHz to
1600 MHz
1350 MHz to
2750 MHz
1450 MHz to
2850 MHz
The ADRF6601 is a high dynamic range active mixer with an
integrated fractional-N phase-locked loop (PLL) and a voltage-
controlled oscillator (VCO) for internal mixer LO generation.
ADRF6602
ADRF6603
Along with the ADRF6602 and the ADRF6603, the ADRF6601
forms a family of integrated PLL/mixers. The ADRF6601 covers
the frequency range of 750 MHz to 1160 MHz.
2600 MHz
3200 MHz
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO
NC NC
10
17
22
27
34
32
33
36
LODRV_EN
LON 37
38
ADRF6601
3.3V
LDO
2
9
DECL3P3
INTERNAL LO RANGE
750MHz TO 1160MHz
BUFFER
BUFFER
2.5V
LDO
DECL2P5
DECLVCO
LOP
VCO
LDO
PLL_EN 16
DIV
2:1
40
BY
4, 2, 1
INTEGER
REG
FRACTION
REG
MUX
12
DATA
MODULUS
SPI
13
14
CLK
LE
INTERFACE
26
29
RF
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
IN
VCO
CORE
IP3SET
×2
N COUNTER
21 TO 123
PRESCALER
÷2
6
8
REF_IN
MUX
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
–
+
PHASE
FREQUENCY
DETECTOR
TEMP
SENSOR
÷4
750µA,
1000µA
5
MUXOUT
4
7
11 15 20 21 23 24 25 28 30 31 35
39
18 19
3
R
CP VTUNE IFP IFN
SET
GND
Figure 1.
Rev. 0
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