Datasheet > ADRF5545A

ADRF5545A

更新时间： 2024-11-28 01:06:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	810K
描述
Dual-Channel, 2.4 GHz to 4.2 GHz Receiver Front End

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ADRF5545A 数据手册

Dual-Channel, 2.4 GHz to 4.2 GHz

Receiver Front End

Data Sheet

ADRF5545A

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Integrated dual-channel RF front end

2-stage LNA and high power SPDT switch

On-chip bias and matching

ADRF5545A

Single supply operation

Gain

High gain mode: 32 dB typical at 3.6 GHz

Low gain mode: 16 dB typical at 3.6 GHz

Low noise figure

High gain mode: 1.45 dB typical at 3.6 GHz

Low gain mode: 1.45 dB typical at 3.6 GHz

High isolation

GND

ANT-CHA

GND

30 GND

29 RXOUT-CHA

28 GND

27 BP-CHA

26 PD-CHAB

25 NIC

24 BP-CHB

23 GND

22 RXOUT-CHB

21 GND

SWCTRL-CHAB

SWVDD-CHAB

GND

ANT-CHB

GND

GND 10

RXOUT-CHA and RXOUT-CHB: 47 dB typical

TERM-CHA and TERM-CHB: 52 dB typical

Low insertion loss: 0.65 dB typical at 3.6 GHz

High power handling at T_CASE= 105°C

Full lifetime

LTE average power (9 dB PAR): 40 dBm

Single event (<10 sec operation)

LTE average power (9 dB PAR): 43 dBm

High OIP3: 32 dBm typical

Figure 1.

Power-down mode and low gain mode for LNA

Low supply current

High gain mode: 86 mA typical at 5 V

Low gain mode: 36 mA typical at 5 V

Power-down mode: 12 mA typical at 5 V

Positive logic control

6 mm × 6 mm, 40-lead LFCSP package

APPLICATIONS

Wireless infrastructure

TDD massive multiple input and multiple output and active

antenna systems

TDD-based communication systems

GENERAL DESCRIPTION

The ADRF5545A is a dual-channel, integrated radio frequency

(RF), front-end multichip module designed for time division

duplexing (TDD) applications that operates from 2.4 GHz to

4.2 GHz. The ADRF5545A is configured in dual channels with

a cascading two-stage low noise amplifier (LNA) and a high

power silicon single-pole, double-throw (SPDT) switch.

36 mA. In power-down mode, the LNAs are turned off and the

device draws 12 mA.

In transmit operation, when RF inputs are connected to a

termination pin (TERM-CHA or TERM-CHB), the switch

provides a low insertion loss of 0.65 dB and handles long-term

evolution (LTE) average power (9 dB peak to average ratio

(PAR)) of 40 dBm for full lifetime operation and 43 dBm for

single event (<10 sec) LNA protection operation.

In high gain mode, the cascaded two-stage LNA and switch

offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB

at 3.6 GHz with an output third-order intercept point (OIP3) of

32 dBm (typical). In low gain mode, one stage of the two-stage

LNA is in bypass, providing 16 dB of gain at a lower current of

The device comes in an RoHS compliant, compact, 6 mm ×

6 mm, 40-lead LFCSP package.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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