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ADRF5547

更新时间: 2024-11-10 14:58:15
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
15页 313K
描述
双通道 3.7 GHz 至 5.3 GHz 接收器前端

ADRF5547 数据手册

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Dual-Channel, 3.7 GHz to 5.3 GHz,  
Receiver Front End  
ADRF5547  
Data Sheet  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
ADRF5547  
Integrated dual-channel RF front end  
2-stage LNA and high power SPDT switch  
On-chip bias and matching  
Single-supply operation  
Gain  
High gain mode: 33 dB typical at 4.6 GHz  
Low gain mode: 18 dB typical at 4.6 GHz  
Low noise figure  
GND  
GND  
ANT-ChA  
GND  
1
2
3
4
5
6
7
8
9
30 GND  
29 RxOUT-ChA  
28 GND  
27 BP-ChA  
26 PD-ChAB  
25 NIC  
24 BP-ChB  
23 GND  
SWCTRL-ChAB  
SWVDD-ChAB  
GND  
High gain mode: 1.6 dB typical at 4.6 GHz  
Low gain mode: 1.6 dB typical at 4.6 GHz  
High channel to channel isolation  
Between RxOUT-ChA and RxOUT-ChB: 45 dB typical  
Between TERM-ChA and TERM-ChB: 53 dB typical  
Low insertion loss: 0.50 dB typical at 4.6 GHz  
High power handling at TCASE = 105°C  
Full lifetime  
ANT-ChB  
GND  
22 RxOUT-ChB  
21 GND  
GND 10  
Figure 1.  
LTE average power (9 dB PAR): 40 dBm  
Single event (<10 sec operation)  
LTE average power (9 dB PAR): 43 dBm  
High OIP3: 31 dBm typical  
Power-down mode and low gain mode for LNA  
Low supply current  
High gain mode: 86 mA typical at 5 V  
Low gain mode: 36 mA typical at 5 V  
Power-down mode: 12 mA typical at 5 V  
Positive logic control  
40-lead, 6 mm × 6 mm LFCSP  
APPLICATIONS  
Wireless infrastructure  
TDD massive multiple input and multiple output (MIMO) and  
active antenna systems  
TDD-based communication systems  
In low gain mode, one stage of the two-stage LNAs is in bypass,  
providing 18 dB gain at lower current of 36 mA. In power-down  
mode, the LNAs are turned off and the device draws 12 mA.  
GENERAL DESCRIPTION  
The ADRF5547 is a dual-channel, integrated RF, front end  
multichip module designed for time division duplexing (TDD)  
applications that operates from 3.7 GHz to 5.3 GHz. The  
ADRF5547 is configured in dual channels with a cascading  
two-stage low noise amplifier (LNA) and a high power silicon,  
single-pole, double-throw (SPDT) switch.  
In transmit operation, when RF inputs are connected to a  
termination pin (TERM-ChA or TERM-ChB), the switch  
provides a low insertion loss of 0.50 dB and handles long term  
evolution (LTE) average power (9 dB peak to average ratio  
(PAR)) of 40 dBm for full lifetime operation and 43 dBm for  
single event (<10 sec) LNA protection operation.  
In high gain mode, the cascaded, two-stage LNA and switch  
offer a low noise figure of 1.6 dB and high gain of 33 dB at  
4.6 GHz with an output third order intercept point (OIP3) of  
31 dBm (typical).  
The device comes in an RoHS compliant, compact, 40-lead,  
6 mm × 6 mm LFCSP.  
Rev. A  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice.  
No license is granted by implication or otherwise under any patent or patent rights of Analog  
Devices. Trademarks and registeredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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