30 MHz Dual Programmable Filters
and Variable Gain Amplifiers
ADRF6510
FEATURES
FUNCTIONAL BLOCK DIAGRAM
ENBL INP1 INM1 VPS COM GNSW OFS1 VPS
Matched pair of programmable filters and VGAs
Continuous gain control range: −5 dB to +45 dB
6-pole filter
1 MHz to 30 MHz in 1 MHz steps, 0.5 dB corner frequency
SPI programmable
VPSD
COMD
LE
OPP1
OPM1
COM
6 dB front-end gain step
CLK
GAIN
VOCM
COM
SPI
IMD3: >55 dBc for 1.5 V p-p composite output
HD2, HD3: >60 dBc for 1.5 V p-p output
Differential input and output
Adjustable output common-mode voltage
Optional dc output offset correction
Power-down feature
ADRF6510
DATA
SDO
COM
VPS
OPM2
OPP2
Single 5 V supply operation
COM INP2 INM2 VPS COM OFDS OFS2 VPS
APPLICATIONS
Figure 1.
Baseband I/Q receivers
Diversity receivers
ADC drivers
GENERAL DESCRIPTION
The ADRF6510 is a matched pair of fully differential low noise
and low distortion programmable filters and variable gain ampli-
fiers (VGAs). Each channel is capable of rejecting large out-of-
band interferers while reliably boosting the wanted signal, thus
reducing the bandwidth and resolution requirements on the
analog-to-digital converters (ADCs). The excellent matching
between channels and their high spurious-free dynamic range
over all gain and bandwidth settings make the ADRF6510 ideal
for quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers.
The variable gain amplifiers that follow the filters provide 50 dB
of continuous gain control with a slope of 30 mV/dB. The output
buffers provide a differential output impedance of 20 ꢀ that is
capable of driving 1.5 V p-p into 1 kꢀ loads. The output common-
mode voltage defaults to VPS/2, but it can be programmed via the
VOCM pin. The built-in dc offset correction loop can be disabled
if dc-coupled operation is desired. The high-pass corner frequency
is defined by external capacitors on the OFS1 and OFS2 pins.
The ADRF6510 operates from a 4.75 V to 5.25 V supply and
consumes a maximum supply current of 258 mA when pro-
grammed to the highest bandwidth setting. When disabled, it
consumes 2 mA. The ADRF6510 is fabricated in an advanced
silicon-germanium BiCMOS process and is available in a
32-lead, exposed paddle LFCSP. Performance is specified over
the −40°C to +85°C temperature range.
The filters provide a six-pole Butterworth response with 0.5 dB
corner frequencies programmable through the SPI port from
1 MHz to 30 MHz in 1 MHz steps. The preamplifier that precedes
the filters offers a pin-programmable option of either 6 dB or
12 dB of gain. The preamplifier sets a differential input imped-
ance of 400 Ω and has a common-mode voltage that defaults
to 2.1 V but can be driven from 1.5 V to 2.5 V.
Rev. 0
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