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ADP175ARMZ-0.8-R7 PDF预览

ADP175ARMZ-0.8-R7

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
20页 600K
描述
500 mA, Low Dropout, CMOS Linear Regulator

ADP175ARMZ-0.8-R7 数据手册

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ADP1715/ADP1716  
THEORY OF OPERATION  
connect a small ceramic capacitor from SS to GND. Upon  
startup, a 1.2 μA current source charges this capacitor. The  
ADP1715 start-up output voltage is limited by the voltage at SS,  
providing a smooth ramp up to the nominal output voltage. The  
soft-start time is calculated by  
The ADP1715/ADP1716 are low dropout, CMOS linear  
regulators that use an advanced, proprietary architecture to  
provide high power supply rejection ratio (PSRR) and excellent  
line and load transient response with just a small 2.2 μF ceramic  
output capacitor. Both devices operate from a 2.5 V to 5.5 V  
input rail and provide up to 500 mA of output current. Supply  
current in shutdown mode is typically 100 nA.  
T
SS = VREF ×(CSS/ISS)  
where:  
SS is the soft-start period.  
(1)  
T
IN  
OUT  
V
C
I
REF is the 0.8 V reference voltage.  
SS is the soft-start capacitance from SS to GND.  
SS is the current sourced from SS (1.2 μA).  
CURRENT LIMIT  
THERMAL PROTECT  
When the ADP1715 is disabled (using EN), the soft-start capacitor  
is discharged to GND through an internal 100 Ω resistor.  
SHUTDOWN  
SS/  
ADJ/  
TRK  
EN  
EN  
SOFT  
START  
REFERENCE  
GND  
Figure 26. Internal Block Diagram  
1
Internally, the ADP1715/ADP1716 consist of a reference, an  
error amplifier, a feedback voltage divider, and a PMOS pass  
transistor. Output current is delivered via the PMOS pass  
device, which is controlled by the error amplifier. The error  
amplifier compares the reference voltage with the feedback  
voltage from the output and amplifies the difference. If the  
feedback voltage is lower than the reference voltage, the gate of  
the PMOS device is pulled lower, allowing more current to pass  
and increasing the output voltage. If the feedback voltage is  
higher than the reference voltage, the gate of the PMOS device  
is pulled higher, allowing less current to pass and decreasing the  
output voltage.  
OUT  
V
V
C
C
= 5V  
IN  
= 3.3V  
OUT  
= 2.2µF  
OUT  
2
= 22nF  
SS  
I
= 500mA  
LOAD  
TIME (4ms/DIV)  
Figure 27. OUT Ramp-Up with External Soft-Start Capacitor  
The ADP1715 adjustable version and the ADP1716 have no  
pins for soft start, so the function is switched to an internal soft-  
start capacitor. This sets the soft-start ramp-up period to  
approximately 24 μs. For the worst-case output voltage of 5 V,  
using the suggested 2.2 μF output capacitor, the resulting input  
inrush current is approximately 460 mA, which is less than the  
maximum 500 mA load current.  
The ADP1715 is available in two versions, one with fixed output  
voltage options and one with an adjustable output voltage. The  
fixed output voltage options are set internally to one of sixteen  
values between 0.75 V and 3.3 V, using an internal feedback  
network. The adjustable output voltage can be set to between  
0.8 V and 5.0 V by an external voltage divider connected from  
OUT to ADJ. The fixed output version of ADP1715 allows for  
connection of an external soft-start capacitor, which controls  
the output voltage ramp during startup. The ADP1716 features  
a track pin and is available with fixed output voltage options. All  
devices are controlled by an enable pin (EN).  
EN  
1
SOFT-START FUNCTION (ADP1715)  
V
V
C
= 5V  
= 1.6V  
IN  
OUT  
OUT  
For applications that require a controlled startup, the ADP1715  
provides a programmable soft-start function. Programmable  
soft start is useful for reducing inrush current upon startup and  
for providing voltage sequencing. To implement soft start,  
2
= 2.2µF  
= 10mA  
OUT  
I
LOAD  
TIME (20µs/DIV)  
Figure 28. OUT Ramp-Up with Internal Soft-Start  
Rev. 0 | Page 10 of 20  
 
 

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