ADMCF341
Special Flash Registers
22pF
CLKOUT
XTAL
The flash module has four nonvolatile 8-bit registers called
special flash registers (SFRs) that are accessible independent of
the main flash array, via the flash programming utility. These
registers are for general-purpose, nonvolatile storage. When
erased, the special flash registers contain all 0s. To read special
flash registers from the user program, call the read_reg routine
contained in ROM. Refer to the ADMCF34x DSP Motor Con-
troller Developers Reference Manual for an example.
10MHz
CLKIN
22pF
ADMCF341
RESET
Figure 4. Basic System Configuration
Clock Signals
Boot-from-Flash Code
A security feature is available in the form of a code that, when
set, causes the processor to execute the program in flash
memory at power-up or reset. In this mode, the flash program-
ming utility and debugger are unable to communicate with the
ADMCF341. Consequently, the contents of the flash memory
can be neither programmed nor read.
The ADMCF341 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMCF341. In this mode, with an external clock signal,
the XTAL pin must be left unconnected. The ADMCF341 uses
an input clock with a frequency equal to half the instruction
rate; a 10 MHz input clock yields a 50 ns processor cycle (which
is equivalent to 20 MHz). Normally, instructions are executed
in a single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the CLKOUT
signal when enabled.
The boot-from-flash code may be set via the flash programming
utility, when the user’s program is thoroughly tested and loaded
into flash program memory at address 0x2200. The user’s program
must contain a mechanism for clearing the boot-from-flash code
if reprogramming the flash memory is desired. The only way to
clear boot-from-flash is from within the user program, by calling
the flash_init or auto_erase_reg routines that are included in the
ROM. The user program must be signaled in some way to call
the necessary routine to clear the boot-from-flash code. An
example would be to detect a high level on a PIO pin during
startup initialization and then call the flash_init or auto_erase_reg
routine. The flash_init routine will erase the entire user program
in flash memory before clearing the boot-from-flash code, thus
ensuring the security of the user program. If security is not a
concern, the auto_erase_reg routine can be used to clear the
boot-from-flash code while leaving the user program intact.
Because the ADMCF341 includes an on-chip oscillator feed-
back circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the
processor’s cycle rate of twice the input frequency.
Refer to the ADMCF34x DSP Motor Controller Developer’s Refer-
ence Manual for further instructions and an example of using the
boot-from-flash code.
Reset
The ADMCF341 DSP core and peripherals must be correctly
reset when the device is powered up to assure proper unitiza-
tion. The ADMCF341 contains an integrated power-on-reset
(POR) circuit that provides a complete system reset on power-
up and power-down. The POR circuit monitors the voltage on
the ADMCF341 VDD pin and holds the DSP core and periph-
erals in reset while VDD is less than the threshold voltage level,
VRST. When this voltage is exceeded, the ADMCF341 is held
in reset for an additional 216 DSP clock cycles (TRST in Fig-
ure 5). During this time (TRST), the supply voltage must reach
the recommended operating condition. On power-down, when
the voltage on the VDD pin falls below VRST –VHYST, the
ADMCF341 will be reset. Also, if the external RESET pin is
actively pulled low at any time after power-up, a complete hard-
ware reset of the ADMCF341 is initiated.
FLASH PROGRAM BOOT SEQUENCE
On power-up or reset, the processor begins instruction execu-
tion at address 0x0800 of internal program ROM. The ROM
monitor program that is located there checks the boot-from-
flash code. If that code is set, the processor jumps to location
0x2200 in external flash program memory, where it expects to
find the user’s application program.
If the boot-from-flash code is not set, the monitor attempts to
boot from an external device as described in the ADMCF34x
DSP Motor Controller Developers Reference Manual.
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMCF341
with an external crystal.
V
RST
V
– V
HYST
RST
V
DD
TRST
RESET
Figure 5. Power-On Reset Operation
–10–
REV. 0
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