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ADF4217LBRU-REEL7 PDF预览

ADF4217LBRU-REEL7

更新时间: 2024-11-04 14:47:39
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
24页 265K
描述
IC PLL FREQUENCY SYNTHESIZER, 3000 MHz, PDSO20, MO-153AC, TSSOP-20, PLL or Frequency Synthesis Circuit

ADF4217LBRU-REEL7 数据手册

 浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第2页浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第3页浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第4页浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第5页浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第6页浏览型号ADF4217LBRU-REEL7的Datasheet PDF文件第7页 
Dual Low Power  
Frequency Synthesizers  
a
ADF4217L/ADF4218L/ADF4219L  
FEATURES  
GENERAL DESCRIPTION  
Total IDD: 7.1 mA  
Bandwidth/RF 3.0 GHz  
ADF4217L/ADF4218L, IF 1.1 GHz  
ADF4219L, IF 1.0 GHz  
2.6 V to 3.3 V Power Supply  
1.8 V Logic Compatibility  
Separate VP Allows Extended Tuning Voltage  
Selectable Dual Modulus Prescaler  
Selectable Charge Pump Currents  
Charge Pump Current Matching of 1%  
3-Wire Serial Interface  
The ADF4217L/ADF4218L/ADF4219L are low power dual  
frequency synthesizers that can be used to implement local  
oscillators in the up-conversion and down-conversion sections  
of wireless receivers and transmitters. They can provide the LO  
for both the RF and IF sections. They consist of a low noise  
digital PFD (phase frequency detector), a precision charge pump,  
programmable reference divider, programmable A and B counters,  
a
and a dual modulus prescaler (P/P + 1). The A and B counters,  
in conjunction with the dual modulus prescaler (P/P + 1),  
implement an N divider (N = BP + A). In addition, the 14-bit  
reference counter (R Counter) allows selectable REFIN fre-  
quencies at the PFD input. A complete PLL (phase-locked  
loop) can be implemented if the synthesizers are used with an  
external loop filter and VCOs (voltage controlled oscillators).  
Power-Down Mode  
APPLICATIONS  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)  
Wireless LANs  
Communications Test Equipment  
Cable TV Tuners (CATV)  
Control of all the on-chip registers is via a simple 3-wire interface  
with 1.8 V compatibility. The devices operate with a power supply  
ranging from 2.6 V to 3.3 V and can be powered down when  
not in use.  
FUNCTIONAL BLOCK DIAGRAM  
ADF4219L ONLY  
NC  
V
1
V
2
V 1  
V 2  
P
DD  
DD  
P
ADF4217L/  
ADF4218L/  
ADF4219L  
N = BP + A  
IF  
11(13)-BIT IF  
B COUNTER  
PHASE  
COMPARATOR  
IF  
A
IN  
CHARGE  
PUMP  
PRESCALER  
CP  
IF  
IF  
B
IN  
6(5)-BIT IF  
A COUNTER  
ADF4217L  
ADF4218L  
ONLY  
IF  
LOCK  
DETECT  
REF  
BUFFER  
IN  
14(15)-BIT IF  
R COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DATA  
REGISTER  
SDOUT  
RF  
14(15)-BIT RF  
R COUNTER  
LOCK  
DETECT  
N = BP + A  
CHARGE  
PUMP  
11(13)-BIT RF  
B COUNTER  
CP  
RF  
RF  
RF  
A
B
IN  
RF  
PHASE  
COMPARATOR  
PRESCALER  
IN  
6(5)-BIT RF  
A COUNTER  
DGND  
AGND  
DGND  
AGND  
IF  
FEATURES IN ( ) REFERTO ADF4219L  
NC = NO CONNECT  
RF  
RF  
IF  
REV. C  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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