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ADF4212LBRU-REEL PDF预览

ADF4212LBRU-REEL

更新时间: 2024-11-04 20:39:23
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
20页 361K
描述
IC PLL FREQUENCY SYNTHESIZER, 2400 MHz, PDSO20, MO-153AC, TSSOP-20, PLL or Frequency Synthesis Circuit

ADF4212LBRU-REEL 数据手册

 浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第2页浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第3页浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第4页浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第5页浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第6页浏览型号ADF4212LBRU-REEL的Datasheet PDF文件第7页 
Dual Low Power PLL  
Frequency Synthesizer  
ADF4212L  
FEATURES  
GENERAL DESCRIPTION  
IDD Total, 7.5 mA  
The ADF4212L is a dual frequency synthesizer that can be used  
to implement local oscillators (LO) in the up-conversion and  
down-conversion sections of wireless receivers and transmitters.  
It can provide the LO for both the RF and IF sections. It con-  
sists of a low noise digital PFD (Phase Frequency Detector), a  
precision charge pump, a programmable reference divider,  
programmable A and B counters, and a dual modulus prescaler  
(P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction  
with the dual modulus prescaler (P/P + 1), implement an N  
divider (N = BP + A). In addition, the 14-bit reference counter  
(R counter) allows selectable REFIN frequencies at the PFD  
input. A complete PLL (Phase-Locked Loop) can be implemented  
if the synthesizer is used with external loop filters and VCOs  
(Voltage Controlled Oscillators).  
Bandwidth RF/IF, 2.4 GHz/1.0 GHz  
2.7 V to 3.3 V Power Supply  
Separate VP Allows Extended Tuning Voltage  
Programmable Dual Modulus Prescaler  
RF and IF: 8/9, 16/17, 32/33, 64/65  
Programmable Charge Pump Currents  
3-Wire Serial Interface  
Analog and Digital Lock Detect  
Fastlock Mode  
Power-Down Mode  
20-Lead TSSOP and 20-Lead MLF Chip Scale Package  
APPLICATIONS  
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)  
Base Stations for Wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless LANS  
Cable TV Tuners (CATV)  
Control of all the on-chip registers is via a simple 3-wire inter-  
face with 1.8 V compatibility. The devices operate with a power  
supply ranging from 2.7 V to 3.3 V and can be powered down  
when not in use.  
Communications Test Equipment  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V 1  
V 2  
P
R
SET  
DD  
DD  
P
ADF4212L  
IF PHASE  
FREQUENCY  
DETECTOR  
REFERENCE  
12-BIT IF  
B-COUNTER  
CHARGE  
PUMP  
CP  
IF  
IF  
IN  
IF  
PRESCALER  
6-BIT IF  
A-COUNTER  
IF CURRENT  
SETTING  
IF  
LOCK  
IFCP3 IFCP2 IFCP1  
DETECT  
REF  
OSCILLATOR  
IN  
14-BIT IF  
R-COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLOCK  
DATA  
LE  
22-BIT  
DATA  
REGISTER  
SDOUT  
RFCP3 RFCP2 RFCP1  
REFERENCE  
RF  
14-BIT RF  
R-COUNTER  
LOCK  
DETECT  
12-BIT RF  
B-COUNTER  
CHARGE  
PUMP  
CP  
RF  
RF  
IN  
RF  
PRESCALER  
RF PHASE  
FREQUENCY  
DETECTOR  
REFERENCE  
6-BIT RF  
A-COUNTER  
R
SET  
FL SWITCH  
FL  
O
O
DGND  
RF  
AGND  
RF  
DGND  
IF  
AGND  
IF  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2003 Analog Devices, Inc. All rights reserved.  

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