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ADF4212LBRUZ

更新时间: 2024-11-04 20:00:03
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
29页 448K
描述
Dual Power PLL Frequency Synthesizer

ADF4212LBRUZ 数据手册

 浏览型号ADF4212LBRUZ的Datasheet PDF文件第2页浏览型号ADF4212LBRUZ的Datasheet PDF文件第3页浏览型号ADF4212LBRUZ的Datasheet PDF文件第4页浏览型号ADF4212LBRUZ的Datasheet PDF文件第5页浏览型号ADF4212LBRUZ的Datasheet PDF文件第6页浏览型号ADF4212LBRUZ的Datasheet PDF文件第7页 
Dual Low Power PLL  
Frequency Synthesizer  
ADF4212L  
Data Sheet  
FEATURES  
GENERAL DESCRIPTION  
IDD total: 7.5 mA  
Bandwidth RF/IF: 2.4 GHz/1.0 GHz  
2.7 V to 3.3 V power supply  
Separate VP allows extended tuning voltage  
Programmable dual modulus prescaler  
RF and IF: 8/9, 16/17, 32/33, 64/65  
Programmable charge pump currents  
3-wire serial interface  
The ADF4212L is a dual frequency synthesizer that can be used  
to implement local oscillators (LO) in the up-conversion and  
down-conversion sections of wireless receivers and transmitters.  
It can provide the LO for both the RF and IF sections. It consists  
of a low noise digital phase frequency detector (PFD), a precision  
charge pump, a programmable reference divider, programmable  
A and B counters, and a dual modulus prescaler (P/P + 1). The  
A (6-bit) and B (12-bit) counters, in conjunction with the dual  
modulus prescaler (P/P + 1), implement an N divider (N = BP +  
A). In addition, the 15-bit reference counter (R counter) allows  
selectable REFIN frequencies at the PFD input. A complete phase-  
locked loop (PLL) can be implemented if the synthesizer is used  
with external loop filters and voltage controlled oscillators (VCOs).  
Analog and digital lock detect  
Fastlock mode  
Power-down mode  
20-lead TSSOP and 20-lead LFCSP packages  
APPLICATIONS  
Control of all the on-chip registers is via a simple 3-wire  
interface with 1.8 V compatibility. The devices operate with a  
power supply ranging from 2.7 V to 3.3 V and can be powered  
down when not in use.  
Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,  
WCDMA)  
Base stations for wireless Radio (GSM, PCS, DCS,  
CDMA, WCDMA)  
Wireless LANS  
Cable TV tuners (CATV)  
Communications test equipment  
FUNCTIONAL BLOCK DIAGRAM  
V
1
V
2
V
1
V
2
R
SET  
DD  
DD  
P
P
ADF4212L  
IF PHASE  
FREQUENCY  
DETECTOR  
REFERENCE  
12-BIT IF  
B-COUNTER  
CHARGE  
PUMP  
CP  
IF  
IF  
IN  
IF  
PRESCALER  
6-BIT IF  
A-COUNTER  
IF CURRENT  
SETTING  
IF  
LOCK  
DETECT  
IFCP3 IFCP2 IFCP1  
REF  
OSCILLATOR  
IN  
15-BIT IF  
R-COUNTER  
OUTPUT  
MUX  
MUXOUT  
CLK  
22-BIT  
DATA  
REGISTER  
DATA  
LE  
SDOUT  
RFCP3 RFCP2 RFCP1  
REFERENCE  
RF  
15-BIT RF  
R-COUNTER  
LOCK  
DETECT  
CHARGE  
PUMP  
12-BIT RF  
B-COUNTER  
CP  
RF  
RF  
IN  
RF  
RF PHASE  
FREQUENCY  
DETECTOR  
PRESCALER  
REFERENCE  
6-BIT RF  
A-COUNTER  
R
SET  
FL SWITCH  
O
FL  
O
DGND  
RF  
AGND  
DGND  
AGND  
RF  
IF  
IF  
Figure 1.  
Rev. E  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2002–2014 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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