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ADF4212BCHIPS PDF预览

ADF4212BCHIPS

更新时间: 2024-12-02 03:20:35
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
12页 87K
描述
IC PHASE DETECTOR, 3000 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit

ADF4212BCHIPS 数据手册

 浏览型号ADF4212BCHIPS的Datasheet PDF文件第2页浏览型号ADF4212BCHIPS的Datasheet PDF文件第3页浏览型号ADF4212BCHIPS的Datasheet PDF文件第4页浏览型号ADF4212BCHIPS的Datasheet PDF文件第5页浏览型号ADF4212BCHIPS的Datasheet PDF文件第6页浏览型号ADF4212BCHIPS的Datasheet PDF文件第7页 
a
PreliminaryTechnicalData  
DualFrequencySynthesizer  
ADF4210/ADF4211/ADF4212/ADF4213  
G E NE R AL D E S C R IP T IO N  
FEATURES  
T he AD F4210/AD F4211/AD F4212/AD F4213 is a  
dual frequency synthesizer which can be used to  
implement local oscillators in the up-conversion and  
down-conversion sections of wireless receivers and  
transmitters. T hey can provide the LO for both the  
RF and IF sections. T hey consist of a low-noise digi-  
tal PFD (Phase Frequency Detector), a precision  
charge pump, a programmable reference divider,  
programmable A and B counters and a dual-modulus  
prescaler (P/P+1). T he A (6-bit) and B (12-bit)  
counters, in conjunction with the dual modulus  
prescaler (P/P+1), implement an N divider (N=  
BP+A). In addition, the 15-bit reference counter (R  
Counter), allows selectable REFIN frequencies at the  
PFD input. A complete PLL (Phase-Locked Loop)  
can be implemented if the synthesizers are used with  
an external loop filter and VCO's (Voltage Controlled  
Oscillators)Control of all the on-chip registers is via  
a simple 3-wire interface. T he devices operate with a  
3V ( ± 10%) or 5V( ± 10%) power supply and can be  
powered down when not in use.  
ADF4210:  
ADF4211:  
ADF4212:  
ADF4213:  
550MHz/ 1.2GHz  
550MHz/ 2.0GHz  
550MHz/ 3.0GHz  
1.0GHz/ 2.5GHz  
+2.7 V to +5.5 V Pow er Supply  
Program m able Dual Modulus Prescaler  
Program m able Charge Pum p Currents  
3-Wire Serial Interface  
Digital Lock Detect  
Pow er Dow n Mode  
APPLICATIONS  
Portable Wireless Com m unications (PCS/ PCN,  
Cordless)  
phone System s  
w orks (WLANs)  
Cordless and Cellular Tele-  
Wireless Local Area Net-  
FUNCTIO NAL BLO CK D IAGRAM  
V
1
V
2
V
1
V 2  
RS ET  
CC  
CC  
P
P
AD F 4210/AD F 4211/  
AD F 4212/AD F 4213  
SWALLOW  
CO NTROL  
15 -BIT IF  
IFIN  
+
-
IF  
N-COUNTER  
PRESCALER  
CHARGE  
PUMP  
CP  
IF  
15-BI IF  
R-COUNTER  
PH ASE  
C OM PAR ATOR  
IF  
LOCK  
DETECT  
OS CILLATOR  
REFIN  
OUTPUT  
M UX  
MUXOUT  
FAST  
CH ARGE  
CLOCK  
DATA  
LE  
24-BIT  
DAT A  
PUMP  
REGISTER  
FLO  
RF  
LOCK  
DE TECT  
18 -BIT RF  
N-COUNTE R  
+
RF  
RFIN  
PRESCALER  
-
CHARGE  
PUMP  
CP  
RF  
15-BIT RF  
R-COUNTER  
PH ASE  
C OM PAR ATOR  
SWALLOW  
CONTRO L  
REV.PrD 07/99  
DGND  
AGND  
DGND  
AGND  
IF  
RF  
RF  
IF  
© Analog Devices, Inc., 1999  
Inform ation furnished by Analog Devices is believed to be accurate and reliable. However,  
no responsibility is assum ed by Analog Devices for its use, nor for any infringem ents of  
patents or other rights of third parties which m ay result from its use. No license is granted  
by im plication or otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 781-329-4700 Fax: 781-326-8703  

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