Fractional-N Frequency Synthesizer
Data Sheet
ADF4153A
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
The ADF4153A is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmit-
ters. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. A sigma-delta (Σ-Δ) based fractional interpolator
allows programmable fractional-N division. The INT, FRAC,
and MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).
Separate VP allows extended tuning voltage
Programmable fractional modulus
Programmable charge pump current
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4106, ADF4110/ADF4111/
ADF4112/ADF4113, and ADF4153
Consistent RF output phase
Loop filter design possible with ADIsimPLL
APPLICATIONS
A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,
SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
SDV
R
SET
DD
DD
P
DD
ADF4153A
REFERENCE
4-BIT
R COUNTER
×2
REF
IN
DOUBLER
+
PHASE
CP
CHARGE
PUMP
FREQUENCY
DETECTOR
V
DD
–
HIGH-Z
DGND
LOCK
DETECT
CURRENT
SETTING
OUTPUT
MUX
V
MUXOUT
DD
R
N
DIV
DIV
RFCP3 RFCP2 RFCP1
RF
RF
A
B
IN
N-COUNTER
IN
THIRD ORDER
FRACTIONAL
INTERPOLATOR
CLK
DATA
LE
FRACTION
REG
MODULUS
REG
INTEGER
REG
24-BIT
DATA
REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. A
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