Data Sheet
ADF4153A
SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF INPUT CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
See Figure 12 for an input circuit
−8 dBm minimum/0 dBm maximum
−10 dBm minimum/0 dBm maximum
0.5
1
4
4
GHz
GHz
For lower frequencies, ensure slew rate
(SR) > 400 V/µs
REFIN CHARACTERISTICS
REFIN Input Frequency
See Figure 11 for an input circuit
10
250
MHz
For f < 10 MHz, use a dc-coupled,
CMOS-compatible square wave;
slew rate > 25 V/µs
Biased at AVDD/21
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
0.7
AVDD
10
100
V p-p
pF
µA
32
MHz
ICP Sink/Source
Programmable; see Figure 19
With RSET = 4.7 kΩ
With RSET = 4.7 kΩ
High Value
Low Value
5
mA
µA
%
kΩ
nA
%
312.5
2.5
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Sink and Source Matching
ICP vs. VCP
With RSET = 4.7 kΩ
3.0
10
1
2
2
2
Sink and source current
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
%
%
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
1.4
1.4
V
V
µA
pF
0.6
1
10
V
V
Open-drain 1 kΩ pull-up to 1.8 V
IOL = 500 µA
0.4
3.3
2.7
V
DVDD, SDVDD
AVDD
VP
IDD
AVDD
5.5
24
V
mA
µA
20
1
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH
Normalized 1/f Noise (PN1_f)3
Phase Noise Performance4
1750 MHz Output5
2
)
−223
−121
dBc/Hz
dBc/Hz
PLL loop BW = 500 kHz
Measured at 10 kHz offset, normalized to 1 GHz
@ VCO output
−107
dBc/Hz
@ 5 kHz offset, 25 MHz PFD frequency
1 AC coupling ensures AVDD/2 bias.
2 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF
and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
4 The phase noise is measured with the EV-ADF4153ASD1Z and the Rohde & Schwarz FSUP spectrum analyzer operating in phase noise mode.
5 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
,
Rev. A | Page 3 of 24
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