Fractional-N Frequency Synthesizer
Data Sheet
ADF4154
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 4 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N-divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R-counter) allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and a voltage-controlled oscillator (VCO).
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106, ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise vs. spurious performance
Fast-lock mode with built-in timer
Loop filter design possible with ADIsimPLL™
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined countdown
time value so that the PLL remains in wide bandwidth mode,
instead of the user having to control this time externally.
APPLICATIONS
Base stations for mobile radio (WiMAX, PHS, GSM, PCS, DCS,
CDMA, PMR, W-CDMA, supercell 3G)
Wireless handsets (PMR, GSM, PCS, DCS, CDMA, WCDMA)
CATV equipment
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
Wireless LANs
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
SDV
R
SET
DD
DD
P
DD
ADF4154
REFERENCE
4-BIT
R COUNTER
+
PHASE
×2
REF
IN
CHARGE
PUMP
FREQUENCY
DETECTOR
–
DOUBLER
CP
V
DD
HIGH Z
DGND
LOCK
DETECT
CURRENT
SETTING
OUTPUT
MUX
MUXOUT
FAST-LOCK
SWITCH
V
RFCP3 RFCP2 RFCP1
DD
R
N
DIV
DIV
RF
RF
A
B
IN
N COUNTER
IN
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG
MODULUS
REG
INTEGER REG
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
AGND
DGND
CPGND
Figure 1.
Rev. C
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