Datasheet > ADCS7476_07

ADCS7476_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
24页	498K
描述
1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP

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ADCS7476_07 数据手册

20057716

FIGURE 10. Entering Shutdown Mode

10.0 EXITING SHUTDOWN MODE

20057717

FIGURE 11. Entering Normal Mode

To exit shutdown mode, bring CS back low. Upon bringing

CS low, the ADCS7476/77/78 will begin powering up. Power

up typically takes 1 µs. This microsecond of power-up delay

results in the first conversion result being unusable. The sec-

ond conversion performed after power-up, however, is valid,

as shown in Figure 11.

version process and managing total power consumption of

the product.

13.1 Power Supply Noise

Since the reference voltage of the ADCS7476/77/78 is the

reference voltage, any noise greater than 1/2 LSB in ampli-

tude will have some effect upon the converter noise perfor-

mance. This effect is proportional to the input voltage level.

The power supply should receive all the considerations of a

reference voltage as far as stability and noise is concerned.

Using the same supply voltage for these devices as is used

for digital components will lead to degraded noise perfor-

mance.

If CS is brought back high before the 10th falling edge of

SCLK, the device will return to shutdown mode. This is done

to avoid accidentally entering normal mode as a result of

noise on the CS line. To exit shutdown mode and remain in

normal mode, CS must be kept low until after the 10th falling

edge of SCLK. The ADCS7476/77/78 will be fully powered-

up after 16 SCLK cycles.

13.2 Digital Output Effect Upon Noise

11.0 POWER-UP TIMING

The charging of any output load capacitance requires current

from the digital supply, V_DD. The current pulses required from

the supply to charge the output capacitance will cause voltage

variations at the ADC supply line. If these variations are large

enough, they could degrade SNR and SINAD performance of

the ADC. Similarly, discharging the output capacitance when

the digital output goes from a logic high to a logic low will dump

current into the die substrate, causing "ground bounce" noise

in the substrate that will degrade noise performance if that

current is large enough. The larger the output capacitance,

the more current flows through the device power supply line

and die substrate and the greater is the noise coupled into the

analog path.

The ADCS7476/77/78 typically requires 1 µs to power up, ei-

ther after first applying V_DD, or after returning to normal mode

from shutdown mode. This corresponds to one "dummy" con-

version for any SCLK frequency within the specifications in

this document. After this first dummy conversion, the AD-

CS7476/77/78 will perform conversions properly. Note that

the t_QUIETtime must still be included between the first dummy

conversion and the second valid conversion.

12.0 STARTUP MODE

When the V_DDsupply is first applied, the ADCS7476/77/78

may power up in either of the two modes: normal or shutdown.

As such, one dummy conversion should be performed after

start-up, exactly as described in Section 11.0 POWER-UP

TIMING. The part may then be placed into either normal mode

or the shutdown mode, as described in Section 8.0 NORMAL

MODE and Section 9.0 SHUTDOWN MODE.

The first solution to keeping digital noise out of the power

supply is to decouple the supply from any other components

or use a separate supply for the ADC. To keep noise out of

the supply, keep the output load capacitance as small as

practical. If the load capacitance is greater than 50 pF, use a

100 Ω series resistor at the ADC output, located as close to

the ADC output pin as practical. This will limit the charge and

discharge current of the output capacitance and improve

noise performance. Since the series resistor and the load ca-

13.0 POWER CONSIDERATIONS

There are three concerns relating to the power supply of these

products: the effects of power supply noise upon the conver-

sion process, the digital output loading effects upon the con-

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与ADCS7476_07相关器件

型号	品牌	获取价格	描述	数据表
ADCS7476AIMF	NSC	获取价格	1MSPS, 12-/10-/8-Bit A/D Converters in 6-Lead SOT-23
ADCS7476AIMF	TI	获取价格	8-Bit A/D Converters
ADCS7476AIMF/NOPB	TI	获取价格	1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125
ADCS7476AIMFE	NSC	获取价格	1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP
ADCS7476AIMFE/NOPB	TI	获取价格	1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125
ADCS7476AIMF-NOPB	TI	获取价格	ADCS7478 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & WSON
ADCS7476AIMFX	NSC	获取价格	1MSPS, 12-/10-/8-Bit A/D Converters in 6-Lead SOT-23
ADCS7476AIMFX	TI	获取价格	8-Bit A/D Converters
ADCS7476AIMFX/NOPB	NSC	获取价格	IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, SOT-23, 6 PIN, Analog t
ADCS7476AIMFX/NOPB	TI	获取价格	8-Bit A/D Converters

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