pacitance form a low frequency pole, verify signal integrity
once the series resistor has been added.
normal mode, execute one dummy conversion followed by
one valid conversion, and then put the part back into shut-
down mode. When this is done, the fraction of time spent in
normal mode may be calculated by multiplying the throughput
(in samples per second) by 2 µs, the time taken to perform
one dummy and one valid conversion. The power consump-
tion can then be found by multiplying the fraction of time spent
in normal mode by the normal mode power consumption fig-
ure. The power dissipated while the part is in shutdown mode
is negligible.
13.3 Power Management
When the ADCS7476/77/78 is operated continuously in nor-
mal mode, throughput up to 1 MSPS can be achieved. The
user may trade throughput for power consumption by simply
performing fewer conversions per unit time, and putting the
ADCS7476/77/78 into shutdown mode between conversions.
This method is not advantageous beyond 350 kSPS through-
put.
For example, to calculate the power consumption at 300
kSPS with VDD = 5V, begin by calculating the fraction of time
spent in normal mode: 300,000 samples/second x 2 µs = 0.6,
or 60%. The power consumption at 300 kSPS is then 60% of
17.5 mW (the maximum power consumption at VDD = 5V) or
10.5 mW.
A plot of maximum power consumption versus throughput is
shown in Figure 12. To calculate the power consumption for
a given throughput, remember that each time the part exits
shutdown mode and enters normal mode, one dummy con-
version is required. Generally, the user will put the part into
20057755
FIGURE 12. Maximum Power Consumption vs. Throughput
14.0 LAYOUT AND GROUNDING
The analog input should be isolated from noisy signal lines to
avoid coupling of spurious signals into the input. Any external
component (e.g., a filter capacitor) connected between the
converter’s input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the
ground plane.
Capacitive coupling between noisy digital circuitry and sensi-
tive analog circuitry can lead to poor performance. The solu-
tion is to keep the analog and digital circuitry separated from
each other and the clock line as short as possible.
Digital circuits create substantial supply and ground current
transients. This digital noise could have significant impact up-
on system noise performance. To avoid performance degra-
dation of the ADCS7476/77/78 due to supply noise, do not
use the same supply for the ADCS7476/77/78 that is used for
digital logic.
We recommend the use of a single, uniform ground plane and
the use of split power planes. The power planes should be
located within the same board layer. All analog circuitry (input
amplifiers, filters, reference components, etc.) should be
placed over the analog power plane. All digital circuitry and I/
O lines should be placed over the digital power plane. Fur-
thermore, all components in the reference circuitry and the
input signal chain that are connected to ground should be
connected together with short traces and enter the analog
ground plane at a single, quiet point.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. However, to maximize accuracy in high
resolution systems, avoid crossing analog and digital lines al-
together. It is important to keep clock lines as short as possi-
ble and isolated from ALL other lines, including other digital
lines. In addition, the clock line should also be treated as a
transmission line and be properly terminated.
21
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