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ADCMP605_15 PDF预览

ADCMP605_15

更新时间: 2024-11-23 01:20:31
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
14页 301K
描述
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V

ADCMP605_15 数据手册

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Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,  
Single-Supply LVDS Comparators  
Data Sheet  
ADCMP604/ADCMP605  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CCO  
Fully specified rail to rail at VCCI = 2.5 V to 5.5 V  
Input common-mode voltage from −0.2 V to VCCI + 0.2 V  
Low glitch LVDS-compatible output stage  
1.6 ns propagation delay  
V
CCI  
(ADCMP605 ONLY)  
V
NONINVERTING  
INPUT  
P
Q OUTPUT  
Q OUTPUT  
37 mW at 2.5 V  
Shutdown pin  
Single-pin control for programmable hysteresis and latch  
Power supply rejection > 60 dB  
ADCMP604/  
ADCMP605  
LVDS  
V
INVERTING  
INPUT  
N
−40°C to +125°C operation  
LE/HYS INPUT  
(ADCMP605  
ONLY)  
S
INPUT  
DN  
APPLICATIONS  
Figure 1.  
High speed instrumentation  
Clock and data signal restoration  
Logic level shifting or translation  
Pulse spectroscopy  
High speed line receivers  
Threshold detection  
Peak and zero-crossing detectors  
High speed trigger circuitry  
Pulse-width modulators  
Current-/voltage-controlled oscillators  
Automatic test equipment (ATE)  
GENERAL DESCRIPTION  
A flexible power supply scheme allows the devices to operate  
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input  
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V  
input signal range. Split input/output supplies, with no sequencing  
restrictions on the ADCMP605, support a wide input signal  
range with greatly reduced power consumption.  
The ADCMP604/ADCMP605 are very fast comparators fabricated  
on the Analog Devices, Inc. proprietary XFCB2 process. These  
comparators are exceptionally versatile and easy to use. Features  
include an input range from VEE − 0.5 V to VCCI + 0.2 V, l ow noi s e ,  
LVDS-compatible output drivers, and TTL/CMOS latch inputs  
with adjustable hysteresis and/or shut-down inputs.  
The LVDS-compatible output stage is designed to drive any  
standard LVDS input. The comparator input stage offers robust  
protection against large input overdrive, and the outputs do not  
phase reverse when the valid input signal range is exceeded. High  
speed latch and programmable hysteresis features are also provided  
in a unique single-pin control option.  
The devices offer 1.5 ns propagation delays with 1 ps rms  
random jitter (RJ). Overdrive and slew rate dispersion are  
typically less than 50 ps.  
The ADCMP604 is available in a 6-lead SC70 package, and the  
ADCMP605 is available in a 12-lead LFCSP.  
Rev. B  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2006–2014 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 

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