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ADCMP606_0610 PDF预览

ADCMP606_0610

更新时间: 2024-11-22 04:04:31
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 355K
描述
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators

ADCMP606_0610 数据手册

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Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,  
Single-Supply CML Comparators  
ADCMP606/ADCMP607  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CCO  
(ADCMP607 ONLY)  
Fully specified rail to rail at VCC = 2.5 V to 5.5 V  
Input common-mode voltage from −0.2 V to VCC + 0.2 V  
CML-compatible output stage  
1.25 ns propagation delay  
50 mW @ 2.5V VCC  
Shutdown pin  
V
CCI  
V
NONINVERTING  
INPUT  
P
Q OUTPUT  
Q OUTPUT  
CML  
ADCMP606/  
ADCMP607  
Single-pin control for programmable hysteresis and latch  
(ADCMP607 only)  
V
INVERTING  
INPUT  
N
Power supply rejection > 60 dB  
−40°C to +125°C operation  
LE/HYS INPUT (ADCMP607 ONLY)  
INPUT (ADCMP607 ONLY)  
S
DN  
APPLICATIONS  
Figure 1.  
High speed instrumentation  
Clock and data signal restoration  
Logic level shifting or translation  
Pulse spectroscopy  
High speed line receivers  
Threshold detection  
Peak and zero-crossing detectors  
High speed trigger circuitry  
Pulse-width modulators  
Current-/voltage-controlled oscillators  
Automatic test equipment (ATE)  
GENERAL DESCRIPTION  
to +5.7 V input signal range. The ADCMP607 features split  
input/output supplies with no sequencing restrictions to  
support a wide input signal range with independent output  
swing control and power savings.  
The ADCMP606 and ADCMP607 are very fast comparators  
fabricated on XFCB2, an Analog Devices, Inc. proprietary  
process. These comparators are exceptionally versatile and easy  
to use. Features include an input range from VEE − 0.5 V to  
V
CC + 0.2 V, low noise, CML-compatible output drivers, and  
The CML-compatible output stage is fully back-matched for  
superior performance. The comparator input stage offers robust  
protection against large input overdrive, and the outputs do not  
phase reverse when the valid input signal range is exceeded. On  
the ADCMP607, latch and programmable hysteresis features are  
also provided with a unique single-pin control option.  
TTL-/CMOS-compatible latch inputs with adjustable hysteresis  
and/or shutdown inputs.  
The devices offer 1.25 ns propagation delay with 2.5 ps rms  
random jitter (RJ). Overdrive and slew rate dispersion are  
typically less than 50 ps.  
The ADCMP606 is available in a 6-lead SC70 package and the  
ADCMP607 is available in a 12-lead LFCSP package.  
A flexible power supply scheme allows the devices to operate  
with a single +2.5 V positive supply and a −0.5 V to +2.7 V  
input signal range up to a +5.5 V positive supply with a −0.5 V  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  

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