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ADCMP573BCPZ-RL7 PDF预览

ADCMP573BCPZ-RL7

更新时间: 2024-11-26 12:32:59
品牌 Logo 应用领域
亚德诺 - ADI 比较器放大器
页数 文件大小 规格书
16页 410K
描述
Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators

ADCMP573BCPZ-RL7 数据手册

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Ultrafast 3.3 V/5 V  
Single-Supply SiGe Comparators  
ADCMP572/ADCMP573  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
3.3 V/5.2 V single-supply operation  
150 ps propagation delay  
V
V
CCO  
CCI  
V
TERMINATION  
15 ps overdrive and slew rate dispersion  
8 GHz equivalent input rise time bandwidth  
80 ps minimum pulse width  
TP  
V
NONINVERTING  
INPUT  
P
Q OUTPUT  
Q OUTPUT  
ADCMP572  
ADCMP573  
CML/  
RSPECL  
35 ps typical output rise/fall  
10 ps deterministic jitter (DJ)  
V
INVERTING  
INPUT  
N
200 fs random jitter (RJ)  
V
TERMINATION  
TN  
On-chip terminations at both input pins  
Robust inputs with no output phase reversal  
Resistor-programmable hysteresis  
Differential latch control  
LE INPUT  
LE INPUT  
HYS  
Figure 1.  
Extended industrial −40°C to +125°C temperature range  
APPLICATIONS  
Clock and data signal restoration and level shifting  
Automatic test equipment (ATE)  
High speed instrumentation  
Pulse spectroscopy  
Medical imaging and diagnostics  
High speed line receivers  
Threshold detection  
Peak and zero-crossing detectors  
High speed trigger circuitry  
GENERAL DESCRIPTION  
The ADCMP572 and ADCMP573 are ultrafast comparators  
fabricated on Analog Devices’ proprietary XFCB3 Silicon  
Germanium (SiGe) bipolar process. The ADCMP572 features  
CML output drivers and latch inputs, and the ADCMP573  
features reduced swing PECL (RSPECL) output drivers and  
latch inputs.  
provided at both inputs with the optional capability to be left  
open (on an individual pin basis) for applications requiring  
high impedance inputs.  
The CML output stage is designed to directly drive 400 mV into  
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.  
The RSPECL output stage is designed to drive 400 mV into  
50 Ω terminated to VCCO − 2 V and is compatible with several  
commonly used PECL logic families. The comparator input  
stage offers robust protection against large input overdrive, and  
the outputs do not phase reverse when the valid input signal  
range is exceeded. High speed latch and programmable  
hysteresis features are also provided.  
Both devices offer 150 ps propagation delay and 80 ps  
minimum pulse width for 10 Gbps operation with 200 fs rms  
random jitter (RJ). Overdrive and slew rate dispersion are  
typically less than 15 ps.  
A flexible power supply scheme allows both devices to operate  
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input  
signal range or with split input/output supplies to support a  
wider −0.2 V to +3.2 V input signal range and an independent  
range of output levels. 50 Ω on-chip termination resistors are  
The ADCMP572 and ADCMP573 are available in a 16-lead  
LFCSP package and have been characterized over an extended  
industrial temperature range of −40°C to +125°C.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No  
licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.  

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