ADCMP341/ADCMP343
APPLICATION INFORMATION
IR3 >> IBIAS
The ADCMP341/ADCMP343 are dual, low power comparators
with a built-in 400 mV reference that operates from 1.7 V to 5.5 V.
The comparators are 0.275% accurate with fully programmable
hysteresis, implemented using a new technique of a three-resistor
string on the input. These open-drain outputs are capable of
sinking up to 40 mA.
R3 is therefore
VREF
R3 =
IR3
Iow R2 can be calculated from the following:
COMPARATORS AND INTERNAL REFERENCE
R3
V
RISING −VFALLING
VFALLING
R2 =
Each of the comparators has one input available externally; the
other comparator inputs are connected internally to the 400 mV
reference. The ADCMP341 has two noninverting comparators
and the ADCMP343 has two inverting comparators.
R1 can then be calculated using the following equation:
⎛
⎞
⎞
⎛
⎜
⎜
⎝
VRISING
VREF
⎜
⎟
⎟
−1 − R2
R1 = R3×
⎟
⎜
⎝
⎟
There are two input pins available to each comparator. However,
these two input pins (± ±Ix_U, ± ±Ix_L) connect to the same
input leg of the comparator via a muxing system. This is to
provide fully programmable rising and falling trip points. The
output of the comparator determines which pin is connected to
the input of the same comparator. Using Figure 28 as an
example, when OUTA is high, +±IA_U is connected to the
comparator input. When the input voltage drops and passes
below the 400 mV reference, the output goes low. This in turn
disconnects +±IA_U from the comparator and connects
+±IA_L. This leg of the string is at a lower voltage and thus
instantaneously the effect of hysteresis is applied. Therefore,
using a resistor string on the input as shown in Figure 28, the
voltages for the rising and falling trip points can be programmed
by selecting the appropriate resistors in the string.
⎠
⎠
where:
REF is the specified on chip reference.
BIAS is the maximum specified input bias current.
R1, R2, and R3 are the three resistors as shown in Figure 28.
R3 is the current flowing through R3.
V
I
I
V
V
FALLING is the desired falling trip voltage and lower of the two.
RISING is the desired rising trip voltage and higher of the two.
V
DD
ADCMP341
VINA
R1
+INA_U
+INA_L
R2
R3
OUTA
POWER SUPPLY
400mV
The ADCMP341/ADCMP343 are designed to operate from 1.7 V
to 5.5 V. A 0.1 μF decoupling capacitor is recommended between
VDD and GID.
Figure 28. Programming Hysteresis Example
LAYOUT RECOMMENDATIONS
INPUTS
Correct layout is very important to increase noise immunity.
Long tracks from the input resistors to the device can lead to
noise being coupled onto the inputs. To avoid this, it is best to
place the input resistors as close as possible to the device. ±t is
also recommended that a GID plane is used under this layout.
The combination of small hysteresis and the use of a large R3
resistor further increases susceptibility to noise. ±n this case, a
decoupling capacitor (CA, CB) may be required on the ± ±Ix_U
node to help reduce any noise. A recommended layout example
can be seen in Figure 29.
The comparator inputs are limited to the maximum VDD voltage
range. The voltage on these inputs can be above VDD but never
above the maximum allowed VDD voltage.
OUTPUTS
The open-drain comparator outputs are limited to the maximum
specified VDD voltage range, regardless of the VDD voltage. These
outputs are capable of sinking up to 40 mA. Outputs can be tied
together to provide a common output signal.
PROGRAMMING HYSTERESIS
V
GND
DD
C1
When choosing the resistor values, the input bias current must
be considered as a potential source of error. Begin by choosing a
resistor value for R3, which takes into account the acceptable
error introduced by the maximum specified input bias current.
To reduce this error, the current flowing through the Resistor R3
should be considerably greater than the input bias current.
OUTA
INA
OUTB
INB
R1A
R1B
R2A
R3A
R2B
R3B
U1
CA
CB
Figure 29. Recommended Layout Example
Rev. 0 | Page 10 of 12
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