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ADC14C105CISQ/NOPB PDF预览

ADC14C105CISQ/NOPB

更新时间: 2024-11-28 19:51:31
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
24页 358K
描述
IC 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC32, 5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LLP-32, Analog to Digital Converter

ADC14C105CISQ/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:HVQCCN, LCC32,.2SQ,20Reach Compliance Code:compliant
ECCN代码:3A991.C.3HTS代码:8542.39.00.01
风险等级:5.31最大模拟输入电压:1.6 V
最小模拟输入电压:1.4 V最长转换时间:0.0666667 µs
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
最大线性误差 (EL):0.0244%湿度敏感等级:3
模拟输入通道数量:1位数:14
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5,3.3 V认证状态:Not Qualified
采样速率:105 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:0.8 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

ADC14C105CISQ/NOPB 数据手册

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August 2007  
ADC14C105  
14-Bit, 95/105 MSPS A/D Converter  
General Description  
Features  
The ADC14C105 is a high-performance CMOS analog-to-  
digital converter capable of converting analog input signals  
into 14-bit digital words at rates up to 105 Mega Samples Per  
Second (MSPS). This converter uses a differential, pipelined  
architecture with digital error correction and an on-chip sam-  
ple-and-hold circuit to minimize power consumption and the  
external component count, while providing excellent dynamic  
performance. A unique sample-and-hold stage yields a full-  
power bandwidth of 1 GHz. The ADC14C105 may be oper-  
ated from a single +3.0V or +3.3V power supply and  
consumes low power.  
1 GHz Full Power Bandwidth  
Internal reference and sample-and-hold circuit  
Low power consumption  
Data Ready output clock  
Clock Duty Cycle Stabilizer  
Single +3.0V or +3.3V supply operation  
Power-down mode  
32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)  
Key Specifications  
A separate +2.5V supply may be used for the digital output  
interface which allows lower power operation with reduced  
noise. A power-down feature reduces the power consumption  
to very low levels while still allowing fast wake-up time to full  
operation. The differential inputs accept a 2V full scale differ-  
ential input swing. A stable 1.2V internal voltage reference is  
provided, or the ADC14C105 can be operated with an exter-  
nal 1.2V reference. Output data format (offset binary versus  
2's complement) and duty cycle stabilizer are pin-selectable.  
The duty cycle stabilizer maintains performance over a wide  
range of clock duty cycles.  
Resolution  
Conversion Rate  
SNR (fIN = 240 MHz)  
SFDR (fIN = 240 MHz)  
Full Power Bandwidth  
Power Consumption  
14 Bits  
105 MSPS  
71 dBFS (typ)  
82 dBFS (typ)  
1 GHz (typ)  
350 mW (typ, VA=3.0V)  
400 mW (typ, VA=3.3V)  
Applications  
The ADC14C105 is available in a 32-lead LLP package and  
operates over the industrial temperature range of −40°C to  
+85°C.  
High IF Sampling Receivers  
Wireless Base Station Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
Connection Diagram  
30017901  
© 2007 National Semiconductor Corporation  
300179  
www.national.com  

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