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ADC14DS080_0712 PDF预览

ADC14DS080_0712

更新时间: 2024-11-27 04:31:19
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器
页数 文件大小 规格书
28页 591K
描述
Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs

ADC14DS080_0712 数据手册

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December 14, 2007  
ADC14DS080  
Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS  
Outputs  
General Description  
Features  
The ADC14DS080 is a high-performance CMOS analog-to-  
digital converter capable of converting two analog input sig-  
nals into 14-bit digital words at rates up to 80 Mega Samples  
Per Second (MSPS). The digital outputs are serialized and  
provided on differential LVDS signal pairs. These converters  
use a differential, pipelined architecture with digital error cor-  
rection and an on-chip sample-and-hold circuit to minimize  
power consumption and the external component count, while  
providing excellent dynamic performance. A unique sample-  
and-hold stage yields a full-power bandwidth of 1 GHz. The  
ADC14DS080 may be operated from a single +3.0V or 3.3V  
power supply. A power-down feature reduces the power con-  
sumption to very low levels while still allowing fast wake-up  
time to full operation. The differential inputs accept a 2V full  
scale differential input swing. A stable 1.2V internal voltage  
reference is provided, or the ADC14DS080 can be operated  
with an external 1.2V reference. Output data format (offset  
binary versus 2's complement) and duty cycle stabilizer are  
selectable. The duty cycle stabilizer maintains performance  
over a wide range of clock duty cycles. A serial interface al-  
lows access to the control registers for full control of the  
ADC14DS80 functionality. The ADC14DS080 is available in  
a 60-lead LLP package and operates over the industrial tem-  
perature range of −40°C to +85°C.  
Clock Duty Cycle Stabilizer  
Single +3.0V or 3.3V supply operation  
Serial LVDS Outputs  
Serial Control Interface  
Overrange outputs  
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)  
Key Specifications  
Resolution  
Conversion Rate  
SNR (fIN = 170 MHz)  
SFDR (fIN = 170 MHz)  
Full Power Bandwidth  
Power Consumption  
14 Bits  
80 MSPS  
72 dBFS (typ)  
82 dBFS (typ)  
1 GHz (typ)  
800 mW (typ)  
Applications  
High IF Sampling Receivers  
Wireless Base Station Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
Connection Diagram  
30035801  
© 2007 National Semiconductor Corporation  
300358  
www.national.com  

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