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ADC14DC080 PDF预览

ADC14DC080

更新时间: 2024-11-27 11:12:47
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
26页 670K
描述
双通道、14 位、80MSPS、1.0GHz 输入带宽模数转换器 (ADC)

ADC14DC080 数据手册

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ADC14DC080  
www.ti.com  
SNAS463B SEPTEMBER 2008REVISED APRIL 2013  
ADC14DC080 Dual 14-Bit, 80 MSPS A/D Converter with CMOS Outputs  
Check for Samples: ADC14DC080  
1
FEATURES  
DESCRIPTION  
The ADC14DC080 is a high-performance CMOS  
analog-to-digital converter capable of converting two  
analog input signals into 14-bit digital words at rates  
up to 80 Mega Samples Per Second (MSPS). These  
converters use a differential, pipelined architecture  
with digital error correction and an on-chip sample-  
and-hold circuit to minimize power consumption and  
the external component count, while providing  
excellent dynamic performance. A unique sample-  
and-hold stage yields a full-power bandwidth of 1  
GHz. The ADC14DC080 may be operated from a  
single +3.0V power supply. A power-down feature  
reduces the power consumption to very low levels  
while still allowing fast wake-up time to full operation.  
2
Internal Sample-and-Hold Circuit and Precision  
Reference  
Low Power Consumption  
Clock Duty Cycle Stabilizer  
Single +3.0V Supply Operation  
Power-Down Mode  
Offset Binary or 2's Complement Output Data  
Format  
60-Pin WQFN Package, (9x9x0.8mm, 0.5mm  
Pin-Pitch)  
APPLICATIONS  
The differential inputs provide  
a 2V full scale  
differential input swing. A stable 1.2V internal voltage  
reference is provided, or the ADC14DC080 can be  
operated with an external 1.2V reference. Output  
data format (offset binary versus 2's complement)  
and duty cycle stabilizer are pin-selectable. The duty  
cycle stabilizer maintains performance over a wide  
range of clock duty cycles.  
High IF Sampling Receivers  
Wireless Base Station Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
KEY SPECIFICATIONS  
The ADC14DC080 is available in a 60-lead WQFN  
package and operates over the industrial temperature  
range of 40°C to +85°C.  
Resolution 14 Bits  
Conversion Rate 80 MSPS  
SNR (fIN = 170 MHz) 71 dBFS (typ)  
SFDR (fIN = 170 MHz) 83 dBFS (typ)  
Full Power Bandwidth 1 GHz (typ)  
Power Consumption 600 mW (typ)  
Block Diagram  
2
14  
14  
14-Bit Pipelined  
ADC Core  
Output  
Buffers  
CHANNEL A  
DA0-DA13  
V
A
IN  
3
Ref.Decoupling  
Reference  
A
V
REF  
Timing  
Generation  
CLK  
DRDY  
Reference  
B
3
2
Ref.Decoupling  
14  
14  
CHANNEL B  
DB0-DB13  
14-Bit Pipelined  
ADC Core  
Output  
Buffers  
V
B
IN  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  

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