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ADC1115S125HN/C1,5 PDF预览

ADC1115S125HN/C1,5

更新时间： 2024-11-09 14:40:47
品牌 Logo 应用领域
艾迪悌 - IDT 转换器
页数 文件大小 规格书
36页 350K
描述
IC,A/D CONVERTER,SINGLE,11-BIT,LLCC,40PIN

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中文翻译

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ADC1115S125HN/C1,5 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFN
包装说明：QCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.83Is Samacsys：N
最大模拟输入电压：5.25 V转换器类型：A/D CONVERTER
JESD-30 代码：S-PQCC-N40JESD-609代码：e3
湿度敏感等级：1位数：11
功能数量：1端子数量：40
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3/5 V
认证状态：Not Qualified子类别：Analog to Digital Converters
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

ADC1115S125HN/C1,5 数据手册

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ADC1115S125  
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS  
DDR digital outputs  
Rev. 03 — 2 July 2012  
Product data sheet  
1. General description  
The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized  
for high dynamic performance and low power consumption at sample rates up to  
125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is  
accurate enough to guarantee zero missing codes over the entire operating range.  
Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in  
CMOS mode, because of a separate digital output supply.  
The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data  
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the  
user to easily configure the ADC.  
The device also includes a SPI programmable full-scale to allow flexible input voltage  
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the  
baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in  
communications, imaging and medical applications - especially in high Intermediate  
Frequency (IF) applications because of the integrated input buffer. The input buffer  
ensures that the input impedance remains constant and low and the performance  
consistent over a wide frequency range.  
2. Features and benefits  
SNR, 66.5 dBFS; SFDR, 86 dBc  
Input bandwidth, 600 MHz  
Power dissipation, 840 mW including  
analog input buffer  
Sample rate up to 125 Msps  
11-bit pipelined ADC core  
Clock input divided by 2 for less jitter  
contribution  
Serial Peripheral Interface (SPI)  
Duty cycle stabilizer  
Integrated input buffer  
Fast OuT-of-Range (OTR) detection  
Flexible input voltage range: 1 V (p-p) to Offset binary, two’s complement, gray  
2 V (p-p)  
code  
CMOS or LVDS DDR digital outputs  
Power-down mode and Sleep mode  
HVQFN40 package  
Pin compatible with the ADC1415S  
series, the ADC1215S series and the  
ADC1015S series  
®
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